Hi Vincent,
Here is an updated version of patch #3.
-Tom
On Fri, Jun 14, 2013 at 08:35:03AM -0700, Vincent Lejeune wrote:
> Hi,
>
> Thank for your work on this !
> Patch 2, 4 and 5 have my rb.
>
>
> >diff --git a/lib/Target/R600/R600InstrInfo.cpp
> >b/lib/Target/R600/R600InstrInfo.cpp
> >index b9da74c..6de47f7 100644
> >--- a/lib/Target/R600/R600InstrInfo.cpp
> >+++ b/lib/Target/R600/R600InstrInfo.cpp
> >@@ -133,6 +133,12 @@ bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
> > bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
> > unsigned TargetFlags = get(Opcode).TSFlags; >+ return (TargetFlags &
> > R600_InstFlag::ALU_INST);
> >+}
> >+
> >+bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
> >+ unsigned TargetFlags = get(Opcode).TSFlags;
> >+
> > return ((TargetFlags & R600_InstFlag::OP1) |
> > (TargetFlags & R600_InstFlag::OP2) |
> > (TargetFlags & R600_InstFlag::OP3));
> Function prototype is not defined here (it is defined in patch 5).
>
>
>
> >diff --git a/lib/Target/R600/R600MachineScheduler.cpp
> >b/lib/Target/R600/R600MachineScheduler.cpp
> >index a330d88..acc1b4d 100644
> >--- a/lib/Target/R600/R600MachineScheduler.cpp
> >+++ b/lib/Target/R600/R600MachineScheduler.cpp
> >@@ -269,10 +269,14 @@ R600SchedStrategy::AluKind
> >R600SchedStrategy::getAluKind(SUnit *SU) const {
> > }
> >
> > // Does the instruction take a whole IG ?
> >+ // XXX: Is it possible to add a helper function in R600InstrInfo that
> >can
> >+ // be used here and in R600PacketizerList::isSoloInstruction() ?
> > if(TII->isVector(*MI) ||
> > TII->isCubeOp(MI->getOpcode()) ||
> >- TII->isReductionOp(MI->getOpcode()))
> >+ TII->isReductionOp(MI->getOpcode()) ||
> >+ MI->getOpcode() == AMDGPU::GROUP_BARRIER) {
> > return AluT_XYZW;
> >+ }
>
> I'm not sure it'll factorize that much code ; R600Packetizer is called after
> cube/reduction op are lowered
> by R600Expand pass and thus the isVector/ReductionOp check is useless. I may
> have left some debug code in
> isSoloInstruction code though.
>
>
>
> ----- Mail original -----
> > De : Tom Stellard <t...@stellard.net>
> > À : llvm-comm...@cs.uiuc.edu
> > Cc : mesa-dev@lists.freedesktop.org
> > Envoyé le : Jeudi 13 juin 2013 2h42
> > Objet : [Mesa-dev] R600 Patches: Add support for the local address space
> >
> > Hi,
> >
> > The attached patches add support for local address space on
> > Evergreen / Northern Islands GPUs.
> >
> > Please Review.
> >
> > -Tom
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
>From e5c9de74bcd7625b954aa3f070e4cb9a4b920c85 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stell...@amd.com>
Date: Wed, 12 Jun 2013 09:02:39 -0700
Subject: [PATCH] R600: Add ALUInst bit to tablegen definitions v2
v2:
- Remove functions left over from a previous rebase.
---
lib/Target/R600/R600Defines.h | 3 ++-
lib/Target/R600/R600InstrFormats.td | 2 ++
lib/Target/R600/R600InstrInfo.cpp | 4 +---
lib/Target/R600/R600Instructions.td | 3 +++
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/Target/R600/R600Defines.h b/lib/Target/R600/R600Defines.h
index e30ea27..6bcf8ae 100644
--- a/lib/Target/R600/R600Defines.h
+++ b/lib/Target/R600/R600Defines.h
@@ -41,7 +41,8 @@ namespace R600_InstFlag {
OP1 = (1 << 10),
OP2 = (1 << 11),
VTX_INST = (1 << 12),
- TEX_INST = (1 << 13)
+ TEX_INST = (1 << 13),
+ ALU_INST = (1 << 14)
};
}
diff --git a/lib/Target/R600/R600InstrFormats.td
b/lib/Target/R600/R600InstrFormats.td
index d31f18c..2c98fb9 100644
--- a/lib/Target/R600/R600InstrFormats.td
+++ b/lib/Target/R600/R600InstrFormats.td
@@ -26,6 +26,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag>
pattern,
bit HasNativeOperands = 0;
bit VTXInst = 0;
bit TEXInst = 0;
+ bit ALUInst = 0;
let Namespace = "AMDGPU";
let OutOperandList = outs;
@@ -47,6 +48,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag>
pattern,
let TSFlags{11} = Op2;
let TSFlags{12} = VTXInst;
let TSFlags{13} = TEXInst;
+ let TSFlags{14} = ALUInst;
}
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/R600/R600InstrInfo.cpp
b/lib/Target/R600/R600InstrInfo.cpp
index d17425f..f267ee9 100644
--- a/lib/Target/R600/R600InstrInfo.cpp
+++ b/lib/Target/R600/R600InstrInfo.cpp
@@ -133,9 +133,7 @@ bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
unsigned TargetFlags = get(Opcode).TSFlags;
- return ((TargetFlags & R600_InstFlag::OP1) |
- (TargetFlags & R600_InstFlag::OP2) |
- (TargetFlags & R600_InstFlag::OP3));
+ return (TargetFlags & R600_InstFlag::ALU_INST);
}
bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
diff --git a/lib/Target/R600/R600Instructions.td
b/lib/Target/R600/R600Instructions.td
index d819d44..b0a82ff 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -114,6 +114,7 @@ class R600_1OP <bits<11> inst, string opName, list<dag>
pattern,
let update_pred = 0;
let HasNativeOperands = 1;
let Op1 = 1;
+ let ALUInst = 1;
let DisableEncoding = "$literal";
let UseNamedOperandTable = 1;
@@ -151,6 +152,7 @@ class R600_2OP <bits<11> inst, string opName, list<dag>
pattern,
let HasNativeOperands = 1;
let Op2 = 1;
+ let ALUInst = 1;
let DisableEncoding = "$literal";
let UseNamedOperandTable = 1;
@@ -193,6 +195,7 @@ class R600_3OP <bits<5> inst, string opName, list<dag>
pattern,
let DisableEncoding = "$literal";
let Op3 = 1;
let UseNamedOperandTable = 1;
+ let ALUInst = 1;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
--
1.7.11.4
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