On Thu, Jun 20, 2013 at 06:43:49PM -0500, Aaron Watry wrote:
> Note: Only adding test for evergreen, not SI yet.
>
> When I attempted to expand vselect for SI, I got the following:
> llc:
> /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522:
> llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*):
> Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
> "Vector compare must return a vector result!"' failed.
>
Can you file a bug for this one too?
Thanks,
Tom
> Signed-off-by: Aaron Watry <awa...@gmail.com>
> ---
> test/CodeGen/R600/vselect.ll | 26 ++++++++++++++++++++------
> 1 file changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll
> index edd7ba0..3f08cec 100644
> --- a/test/CodeGen/R600/vselect.ll
> +++ b/test/CodeGen/R600/vselect.ll
> @@ -1,10 +1,24 @@
> -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK
> %s
>
> -; CHECK: @test_select_v4i32
> -; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> -; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> -; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> -; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +;EG-CHECK: @test_select_v2i32
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +
> +define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32>
> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
> +entry:
> + %0 = load <2 x i32> addrspace(1)* %in0
> + %1 = load <2 x i32> addrspace(1)* %in1
> + %cmp = icmp ne <2 x i32> %0, %1
> + %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
> + store <2 x i32> %result, <2 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +;EG-CHECK: @test_select_v4i32
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
> +;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
> T[0-9]+\.[XYZW]}}
>
> define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32>
> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
> entry:
> --
> 1.8.1.2
>
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