On Thu, Jun 13, 2013 at 2:55 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be attempted to generalize
> the source register type assertions to allow D and UD. However, the
> src1 and src2 assertions actually checked src0.type against D and UD due
> to a copy and paste bug.
>
> It also began setting the source and destination register types based on
> dest.type, ignoring src0/src1/src2.type completely. BFE and BFI2 may
> actually pass mixed D/UD types and expect them to be ignored, which is
> arguably a bit sloppy, but not too crazy either.
>
> This patch simply removes the source register assertions as those values
> aren't used anyway. It also clarifies the comment above the block that
> sets the register types.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 19 +++++--------------
> 1 file changed, 5 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 3d0db1b..f2cacd1 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -811,9 +811,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src0.file == BRW_GENERAL_REGISTER_FILE);
> assert(src0.address_mode == BRW_ADDRESS_DIRECT);
> assert(src0.nr < 128);
> - assert(src0.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
> insn->bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
> insn->bits2.da3src.src0_reg_nr = src0.nr;
> @@ -824,9 +821,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src1.file == BRW_GENERAL_REGISTER_FILE);
> assert(src1.address_mode == BRW_ADDRESS_DIRECT);
> assert(src1.nr < 128);
> - assert(src1.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
> insn->bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) & 0x3;
> insn->bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) >> 2;
> @@ -838,9 +832,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src2.file == BRW_GENERAL_REGISTER_FILE);
> assert(src2.address_mode == BRW_ADDRESS_DIRECT);
> assert(src2.nr < 128);
> - assert(src2.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
> insn->bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
> insn->bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
> @@ -849,12 +840,12 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> insn->bits1.da3src.src2_negate = src2.negate;
>
> if (intel->gen >= 7) {
> - /* For MAD and LRP, all incoming src types are float, but for BFE and
> - * BFI2, the three source types might not all be the same. src2, the
> - * primary argument, should match the type of the destination.
> + /* Set both the source and destination types based on dest.type,
> + * ignoring the source register types. The MAD and LRP emitters ensure
> + * that all four types are float. The BFE and BFI2 emitters, however,
> + * may send us mixed D and UD types and want us to ignore that and use
> + * the destination type.
> */
> - assert(dest.type == src2.type);
> -
> switch (dest.type) {
> case BRW_REGISTER_TYPE_F:
> insn->bits1.da3src.src_type = BRW_3SRC_TYPE_F;
> --
> 1.8.3
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Changes look good to me.
Both patches are: Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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