Am Freitag, 24. Mai 2013, 14:07:29 schrieb Tom Stellard:
> From: Tom Stellard <thomas.stell...@amd.com>
>
> ---
> src/gallium/drivers/radeonsi/radeonsi_compute.c | 38
> ++++++++++++++++++------- 1 file changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/radeonsi_compute.c
> b/src/gallium/drivers/radeonsi/radeonsi_compute.c index 035076d..3abf50b
> 100644
> --- a/src/gallium/drivers/radeonsi/radeonsi_compute.c
> +++ b/src/gallium/drivers/radeonsi/radeonsi_compute.c
> @@ -91,9 +91,12 @@ static void radeonsi_launch_grid(
> struct r600_context *rctx = (struct r600_context*)ctx;
> struct si_pipe_compute *program = rctx->cs_shader_state.program;
> struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
> - struct si_resource *input_buffer;
> - uint32_t input_offset = 0;
> - uint64_t input_va;
> + struct si_resource *kernel_args_buffer;
You should initialize this pointer to 0.
> + unsigned kernel_args_size;
> + unsigned num_work_size_bytes = 36;
> + uint32_t kernel_args_offset = 0;
> + uint32_t *kernel_args;
> + uint64_t kernel_args_va;
> uint64_t shader_va;
> unsigned arg_user_sgpr_count = 2;
> unsigned i;
> @@ -112,16 +115,29 @@ static void radeonsi_launch_grid(
> si_pm4_inval_shader_cache(pm4);
> si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
>
> - /* Upload the input data */
> - r600_upload_const_buffer(rctx, &input_buffer, input,
> - program->input_size, &input_offset);
> - input_va = r600_resource_va(ctx->screen, (struct
> pipe_resource*)input_buffer); - input_va += input_offset;
> + /* Upload the kernel arguments */
>
> - si_pm4_add_bo(pm4, input_buffer, RADEON_USAGE_READ);
> + /* The extra num_work_size_bytes are for work group / work item size
> information */ + kernel_args_size = program->input_size +
> num_work_size_bytes;
> + kernel_args = MALLOC(kernel_args_size);
> + for (i = 0; i < 3; i++) {
> + kernel_args[i] = grid_layout[i];
> + kernel_args[i + 3] = grid_layout[i] * block_layout[i];
> + kernel_args[i + 6] = block_layout[i];
> + }
> +
> + memcpy(kernel_args + (num_work_size_bytes / 4), input,
> program->input_size); +
> + r600_upload_const_buffer(rctx, &kernel_args_buffer, kernel_args,
> + kernel_args_size, &kernel_args_offset);
> + kernel_args_va = r600_resource_va(ctx->screen,
> + (struct pipe_resource*)kernel_args_buffer);
> + kernel_args_va += kernel_args_offset;
> +
> + si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
>
> - si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, input_va);
> - si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4,
> S_008F04_BASE_ADDRESS_HI (input_va >> 32) | S_008F04_STRIDE(0));
> + si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
> + si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4,
> S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
>
> si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
> si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
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