This series, available at git://people.freedesktop.org/~mattst88/mesa arb_gpu_shader5
adds support for the bit built-ins for ARB_gpu_shader5 to the GLSL compiler and the i965 driver. Interesting parts of the series - - New IR operations for each built-in, plus two operations that match i965 and Radeon hardware. - 3x new lowering passes, for bitfieldInsert to BFM/BFI instructions, bitfieldInsert to BFM/bitops (for i965 VS), and bitfieldExtract to bitops (for i965 VS). - Addition of 3-src destination and shared-source fields and types on i965 to accommodate the BFE and BFI2 instructions. - Don't bother scalarizing the BFI1 (BFM) instruction in the i965 FS, since a single BFM generated from bitfieldInsert() feeds multiple scalarized BFI2 (BFI) instructions. Potential improvements: - Make 3-source instructions work in the i965 VS, and simply use BFE and BFI2 (and remove two of the lowering passes). - Alternatively, optimize the code generated by the lowering passes - Emit 3-src instructions if working on scalar data. - Do a slightly more efficient lowering if the data type is unsigned. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
