This puts the rounding-up logic into the function itself instead of all
the callers having to manage it. Also drop an "unused" comment in gen4,
as the stride *is* used for texbos (and will be for uniforms soon).
NOTE: This is a candidate for the 9.1 branch.
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 7 +++----
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +++++++---------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 8 +++++---
src/mesa/drivers/dri/intel/intel_context.h | 2 +-
4 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 2aefc0c..6c0b690 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -68,9 +68,9 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
/* _NEW_PROGRAM_CONSTANTS */
drm_intel_bo_unreference(brw->vs.const_bo);
+ uint32_t size = brw->vs.prog_data->nr_pull_params * 4;
brw->vs.const_bo = drm_intel_bo_alloc(intel->bufmgr, "vp_const_buffer",
- brw->vs.prog_data->nr_pull_params * 4,
- 64);
+ size, 64);
drm_intel_gem_bo_map_gtt(brw->vs.const_bo);
for (i = 0; i < brw->vs.prog_data->nr_pull_params; i++) {
@@ -90,8 +90,7 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo);
const int surf = SURF_INDEX_VERT_CONST_BUFFER;
- intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0,
- ALIGN(brw->vs.prog_data->nr_pull_params,
4) / 4,
+ intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
&brw->vs.surf_offset[surf]);
brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 932e472..98eed15 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -916,11 +916,13 @@ void
brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
+ uint32_t size,
uint32_t *out_offset)
{
struct intel_context *intel = &brw->intel;
- const GLint w = width - 1;
+ uint32_t stride = 16;
+ uint32_t elements = ALIGN(size, stride) / stride;
+ const GLint w = elements - 1;
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -939,7 +941,7 @@ brw_create_constant_surface(struct brw_context *brw,
((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
- (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
+ (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
surf[5] = 0;
@@ -1086,8 +1088,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
}
drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
- intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
- ALIGN(brw->wm.prog_data->nr_pull_params,
4) / 4,
+ intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
&brw->wm.surf_offset[surf_index]);
brw->state.dirty.brw |= BRW_NEW_SURFACES;
@@ -1439,11 +1440,8 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
* glBindBufferRange case is undefined, we can just bind the whole buffer
* glBindBufferBase wants and be a correct implementation.
*/
- int size = bo->size - binding->Offset;
- size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
-
intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
- size,
+ bo->size - binding->Offset,
&surf_offsets[i]);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index db04253..484afcd 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -383,11 +383,13 @@ static void
gen7_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
+ uint32_t size,
uint32_t *out_offset)
{
struct intel_context *intel = &brw->intel;
- const GLint w = width - 1;
+ uint32_t stride = 16;
+ uint32_t elements = ALIGN(size, stride) / stride;
+ const GLint w = elements - 1;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, out_offset);
@@ -403,7 +405,7 @@ gen7_create_constant_surface(struct brw_context *brw,
surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
- (16 - 1); /* stride between samples */
+ (stride - 1);
if (intel->is_haswell) {
surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
diff --git a/src/mesa/drivers/dri/intel/intel_context.h
b/src/mesa/drivers/dri/intel/intel_context.h
index 2df15d4..bb21f55 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -202,7 +202,7 @@ struct intel_context
void (*create_constant_surface)(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
+ uint32_t size,
uint32_t *out_offset);
/** \} */
} vtbl;
--
1.7.10.4
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