From: Christian König <christian.koe...@amd.com>
Fixing asm operation names.
Signed-off-by: Christian König <christian.koe...@amd.com>
---
lib/Target/R600/SIISelLowering.cpp | 3 ---
lib/Target/R600/SIInstrInfo.td | 37 ++++++++++++++++++------------------
2 files changed, 18 insertions(+), 22 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 4085890..5a468ae 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -75,7 +75,6 @@ MachineBasicBlock *
SITargetLowering::EmitInstrWithCustomInserter(
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addImm(0x80) // SRC1
- .addImm(0x80) // SRC2
.addImm(0) // ABS
.addImm(1) // CLAMP
.addImm(0) // OMOD
@@ -88,7 +87,6 @@ MachineBasicBlock *
SITargetLowering::EmitInstrWithCustomInserter(
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addImm(0x80) // SRC1
- .addImm(0x80) // SRC2
.addImm(1) // ABS
.addImm(0) // CLAMP
.addImm(0) // OMOD
@@ -101,7 +99,6 @@ MachineBasicBlock *
SITargetLowering::EmitInstrWithCustomInserter(
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
.addImm(0x80) // SRC1
- .addImm(0x80) // SRC2
.addImm(0) // ABS
.addImm(0) // CLAMP
.addImm(0) // OMOD
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index dbe616d..be791e2 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -123,29 +123,28 @@ multiclass VOP1_32 <bits<8> op, string opName, list<dag>
pattern>
multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
: VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
-class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
- string opName, list<dag> pattern> :
- VOP2 <
- op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
- >;
-
-multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
-
- def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
-
- def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
+multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
+ string opName, list<dag> pattern> {
+ def _e32 : VOP2 <
+ op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName#"_e32", pattern
>;
+ def _e64 : VOP3 <
+ {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+ (outs vrc:$dst),
+ (ins arc:$src0, vrc:$src1,
+ i32imm:$abs, i32imm:$clamp,
+ i32imm:$omod, i32imm:$neg),
+ opName#"_e64", []
+ > {
+ let SRC2 = 0x80;
+ }
}
-multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
- def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
+multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
+ : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
- def _e64 : VOP3_64 <
- {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
- >;
-}
+multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
+ : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
: SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
--
1.7.10.4
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