On 6 February 2013 23:26, Kenneth Graunke <kenn...@whitecape.org> wrote:
> Untyped Atomic Operation messages are illegal for non-RAW formats.
> I have no idea why it worked before; the documentation claims it
> shouldn't be allowed and the simulator enforces it.
>
> Some arithmetic sleight of hand happens in this patch:
>
> Previously, we allocated a R32G32B32A32 buffer. However, atomic
> operations only access the first DWord (the 'R' channel). Thus, we
> multiplied all of our offsets (measured in DWords) by 4 to skip over
> the other three channels.
>
> Now, we allocate a single component (effectively R32) buffer,
> eliminating the wasted space. Using the RAW format means that our
> offsets must be measured in bytes (and must be DWord-aligned). This
> means that the multiplication by 4 is still necessary. However, instead
> of skipping over the BGA components, it converts DWords to bytes.
>
> We ought to change the size of the buffer, but I'm pretty sure it was
> just wrong before: brw->shader_time.bo->size is measured in bytes, so
> we were allocating it too large in the past.
>
> NOTE: This is a candidate for the 9.1 branch.
> Cc: Eric Anholt <e...@anholt.net>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
>
Thanks for explaining the arithmetic sleight of hand here :) This patch is:
Reviewed-by: Paul Berry <stereotype...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5 ++---
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 849d127..6652cad 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -437,6 +437,7 @@
> #define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED 0x1B9
> #define BRW_SURFACEFORMAT_B10G10R10A2_UINT 0x1BA
> #define BRW_SURFACEFORMAT_B10G10R10A2_SINT 0x1BB
> +#define BRW_SURFACEFORMAT_RAW 0x1FF
> #define BRW_SURFACE_FORMAT_SHIFT 18
> #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> index 6a4c009..5cf9da0 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> @@ -435,15 +435,14 @@ gen7_create_shader_time_surface(struct brw_context
> *brw, uint32_t *out_offset)
> 8 * 4, 32, out_offset);
>
> surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
> - BRW_SURFACEFORMAT_R32G32B32A32_FLOAT <<
> BRW_SURFACE_FORMAT_SHIFT |
> + BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
> BRW_SURFACE_RC_READ_WRITE;
>
> surf[1] = brw->shader_time.bo->offset; /* reloc */
>
> surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
> SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
> - surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
> - (16 - 1); /* stride between samples */
> + surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH);
>
> /* Emit relocation to surface contents. Section 5.1.1 of the gen4
> * bspec ("Data Cache") says that the data cache does not exist as
> --
> 1.8.1.1
>
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