From: Christian König <christian.koe...@amd.com>
Signed-off-by: Christian König <christian.koe...@amd.com>
---
lib/Target/R600/SIInstrInfo.td | 10 ++++++++++
lib/Target/R600/SIInstructions.td | 19 ++++++++-----------
lib/Target/R600/SILowerLiteralConstants.cpp | 1 -
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 8ff2d6d..baa7956 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -38,6 +38,16 @@ def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
>;
+// Transformation function, extract the lower 32bit of a 64bit immediate
+def LO32 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
+}]>;
+
+// Transformation function, extract the upper 32bit of a 64bit immediate
+def HI32 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
+}]>;
+
class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
AMDGPUInst<outs, ins, asm, pattern> {
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index 85bb73a..f3238fc 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1017,19 +1017,16 @@ def S_MOV_IMM_I32 : InstSI <
[(set SReg_32:$dst, (imm:$src0))]
>;
-// i64 immediates aren't really supported in hardware, but LLVM will use the
i64
-// type for indices on load and store instructions. The pattern for
-// S_MOV_IMM_I64 will only match i64 immediates that can fit into 32-bits,
-// which the hardware can handle.
-def S_MOV_IMM_I64 : InstSI <
- (outs SReg_64:$dst),
- (ins i64imm:$src0),
- "S_MOV_IMM_I64 $dst, $src0",
- [(set SReg_64:$dst, (IMM32bitIn64bit:$src0))]
->;
-
} // End isCodeGenOnly, isPseudo = 1
+// i64 immediates aren't supported in hardware, split it into two 32bit values
+def : Pat <
+ (i64 imm:$imm),
+ (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+ (S_MOV_IMM_I32 (LO32 imm:$imm)), low),
+ (S_MOV_IMM_I32 (HI32 imm:$imm)), high)
+>;
+
class SI_LOAD_LITERAL<Operand ImmType> :
Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> {
diff --git a/lib/Target/R600/SILowerLiteralConstants.cpp
b/lib/Target/R600/SILowerLiteralConstants.cpp
index 2d5ab0b..e6cce91 100644
--- a/lib/Target/R600/SILowerLiteralConstants.cpp
+++ b/lib/Target/R600/SILowerLiteralConstants.cpp
@@ -73,7 +73,6 @@ bool
SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
switch (MI.getOpcode()) {
default: break;
case AMDGPU::S_MOV_IMM_I32:
- case AMDGPU::S_MOV_IMM_I64:
case AMDGPU::V_MOV_IMM_F32:
case AMDGPU::V_MOV_IMM_I32: {
unsigned MovOpcode;
--
1.7.9.5
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