---
lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 6 +++---
lib/Target/AMDGPU/AMDILISelLowering.cpp | 3 ++-
lib/Target/AMDGPU/R600Instructions.td | 6 +++---
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 7307449..5bde9db 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -167,9 +167,9 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
Op.getOperand(1));
SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
Op.getOperand(3));
- return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
- Op.getOperand(2),
- OneSubAC);
+ return DAG.getNode(ISD::FADD, DL, VT,
+ DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
+ OneSubAC);
}
diff --git a/lib/Target/AMDGPU/AMDILISelLowering.cpp
b/lib/Target/AMDGPU/AMDILISelLowering.cpp
index ce7a5e8..157e3b5 100644
--- a/lib/Target/AMDGPU/AMDILISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDILISelLowering.cpp
@@ -472,7 +472,8 @@ AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG
&DAG) const
SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
// float fr = mad(fqneg, fb, fa);
- SDValue fr = DAG.getNode(AMDGPUISD::MAD, DL, FLTTY, fqneg, fb, fa);
+ SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
+ DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
// int iq = (int)fq;
SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
diff --git a/lib/Target/AMDGPU/R600Instructions.td
b/lib/Target/AMDGPU/R600Instructions.td
index b0c1628..9259680 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -553,8 +553,8 @@ let Predicates = [isR600toCayman] in {
def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
// Non-IEEE MUL: 0 * anything = 0
-def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
-def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
+def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", fmul>;
+def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", int_AMDGPU_mul>;
def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
@@ -796,7 +796,7 @@ class MUL_LIT_Common <bits<5> inst> : R600_3OP <
class MULADD_Common <bits<5> inst> : R600_3OP <
inst, "MULADD",
[(set (f32 R600_Reg32:$dst),
- (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
+ (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
>;
class CNDE_Common <bits<5> inst> : R600_3OP <
--
1.8.0
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