[Mesa-dev] [PATCH 1/2] radeon/llvm: interp instructions emits native outputs

[Vincent Lejeune]

---
 lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 11 ++++-----
 lib/Target/AMDGPU/R600Instructions.td         | 33 ++++++++++++++++++++++++---
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 
b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
index f499c78..5c5f407 100644
--- a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
+++ b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
@@ -95,8 +95,8 @@ bool 
R600ExpandSpecialInstrsPass::ExpandInputPerspective(MachineInstr &MI)
   for (unsigned i = 0; i < 8; i++) {
     unsigned IJIndex = AMDGPU::R600_TReg32RegClass.getRegister(
         2 * IJIndexBase + ((i + 1) % 2));
-    unsigned ReadReg = AMDGPU::R600_TReg32RegClass.getRegister(
-        4 * MI.getOperand(2).getImm());
+    unsigned ReadReg = 448 + MI.getOperand(2).getImm();
+
 
     unsigned Sel;
     switch (i % 4) {
@@ -117,7 +117,7 @@ bool 
R600ExpandSpecialInstrsPass::ExpandInputPerspective(MachineInstr &MI)
         I, MI.getParent()->findDebugLoc(I),
         Opcode, Res)
         .addReg(IJIndex)
-        .addReg(ReadReg)
+        .addImm(ReadReg)
         .addImm(0);
 
     if (!(i> 1 && i < 6)) {
@@ -143,8 +143,7 @@ bool 
R600ExpandSpecialInstrsPass::ExpandInputConstant(MachineInstr &MI)
   unsigned DstReg = MI.getOperand(0).getReg();
 
   for (unsigned i = 0; i < 4; i++) {
-    unsigned ReadReg = AMDGPU::R600_TReg32RegClass.getRegister(
-        4 * MI.getOperand(1).getImm() + i);
+    unsigned ReadReg = 448 + MI.getOperand(1).getImm();
 
     unsigned Sel;
     switch (i % 4) {
@@ -160,7 +159,7 @@ bool 
R600ExpandSpecialInstrsPass::ExpandInputConstant(MachineInstr &MI)
     MachineInstr *NewMI = BuildMI(*(MI.getParent()),
         I, MI.getParent()->findDebugLoc(I),
         TII->get(AMDGPU::INTERP_LOAD_P0), Res)
-        .addReg(ReadReg)
+        .addImm(ReadReg)
         .addImm(0);
 
     if (i % 4 !=  3)
diff --git a/lib/Target/AMDGPU/R600Instructions.td 
b/lib/Target/AMDGPU/R600Instructions.td
index e6e8728..dbcdc2b 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -297,29 +297,56 @@ def input_constant :  AMDGPUShaderInst <
 
 def INTERP_XY : InstR600 <0xD6,
   (outs R600_Reg32:$dst),
-  (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
+  (ins R600_Reg32:$src, i32imm:$arraybase, i32imm:$flags),
   "INTERP_XY dst",
   [], AnyALU>
 {
   let FlagOperandIdx = 3;
+  bits<9> arraybase;
+  bits<7> dst;
+  bits<9> src;
+  bits<11> inst;
+  let Inst{8-0}   = src;
+  let Inst{49-39} = 0xD6;
+  let Inst{59-53} = dst;
+
+  let Inst{21-13} = arraybase;
+  let Inst{52-50} = 5; // Bank Swizzle
 }
 
 def INTERP_ZW : InstR600 <0xD7,
   (outs R600_Reg32:$dst),
-  (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
+  (ins R600_Reg32:$src, i32imm:$arraybase, i32imm:$flags),
   "INTERP_ZW dst",
   [], AnyALU>
 {
   let FlagOperandIdx = 3;
+  bits<9> arraybase;
+  bits<7> dst;
+  bits<9> src;
+  bits<11> inst;
+  let Inst{8-0}   = src;
+  let Inst{49-39} = 0xD7;
+  let Inst{59-53} = dst;
+
+  let Inst{21-13} = arraybase;
+  let Inst{52-50} = 5; // Bank Swizzle
 }
 
 def INTERP_LOAD_P0 : InstR600 <0xE0,
   (outs R600_Reg32:$dst),
-  (ins R600_Reg32:$src, i32imm:$flags),
+  (ins i32imm:$arraybase, i32imm:$flags),
   "INTERP_LOAD_P0 dst",
   [], AnyALU>
 {
   let FlagOperandIdx = 2;
+  bits<9> arraybase;
+  bits<7> dst;
+  bits<11> inst;
+
+  let Inst{49-39} = 0xE0;
+  let Inst{59-53} = dst;
+  let Inst{8-0} = arraybase;
 }
 
 let Predicates = [isR600toCayman] in { 
-- 
1.7.11.7

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