On Fri, Oct 05, 2012 at 05:08:04PM -0700, Kenneth Graunke wrote:
> According to internal bug reports, guardband clipping sometimes
> incorrectly discards triangles unless bit 5 of 3D_CHICKEN3 ("SF Disable
> fastclip optimization when culled") is set.
>
> Experimentally, this appears to be true. With guardband clipping
> enabled, Dante randomly loses triangles unless bit 5 is set.
>
> The BSpec indicates that the default value of the register is supposed
> to be 0x20 (just bit 5), but on my Lenovo X220 it appears to be 0.
>
> Daniel attempted to implement the workaround via a kernel patch named
> drm/i915: implement w/a for incorrect guarband clipping
> but unfortunately, the write isn't taking effect for some reason.
>
> Fixes clipping issues in Dante.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53946
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55523
> Cc: Oliver McFadden <oliver.mcfad...@linux.intel.com>
> Cc: nkalk...@web.de
> Cc: Eric Anholt <e...@anholt.net>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Does this really work as advertised?
The reg_read_ioctl is brand-new, only merged into 3.7. And it has a
whitelist of registers that userspace is allowed to read, and CHICKEN_3 is
not on it.
-Daniel
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 11 +++++++++++
> src/mesa/drivers/dri/i965/brw_context.h | 1 +
> src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 +-
> src/mesa/drivers/dri/intel/intel_reg.h | 3 +++
> 4 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index e94df26..d73aafd 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -43,6 +43,7 @@
>
> #include "intel_fbo.h"
> #include "intel_mipmap_tree.h"
> +#include "intel_reg.h"
> #include "intel_regions.h"
> #include "intel_span.h"
> #include "intel_tex.h"
> @@ -355,6 +356,16 @@ brwCreateContext(int api,
> brw->needs_unlit_centroid_workaround = true;
> }
>
> + if (intel->gen == 6) {
> + /* On Sandybridge, guardband clipping causes random triangles to be
> + * discarded unless bit 5 of 3D_CHICKEN3 is set.
> + */
> + uint64_t chicken;
> + brw->has_working_guardband =
> + drm_intel_reg_read(intel->bufmgr, _3D_CHICKEN3, &chicken) == 0 &&
> + (chicken & _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
> + }
> +
> brw->prim_restart.in_progress = false;
> brw->prim_restart.enable_cut_index = false;
> intel->hw_ctx = drm_intel_gem_context_create(intel->bufmgr);
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 3dac633..2e74949 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -750,6 +750,7 @@ struct brw_context
> bool has_surface_tile_offset;
> bool has_compr4;
> bool has_negative_rhw_bug;
> + bool has_working_guardband;
> bool has_aa_line_parameters;
> bool has_pln;
> bool precompile;
> diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c
> b/src/mesa/drivers/dri/i965/gen6_clip_state.c
> index c34d87e..294d7a9 100644
> --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
> @@ -74,7 +74,7 @@ upload_clip_state(struct brw_context *brw)
> GEN6_CLIP_MODE_NORMAL |
> nonperspective_barycentric_enable_flag |
> GEN6_CLIP_XY_TEST |
> - GEN6_CLIP_GB_TEST |
> + (brw->has_working_guardband ? GEN6_CLIP_GB_TEST : 0) |
> userclip << GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT |
> depth_clamp |
> provoking);
> diff --git a/src/mesa/drivers/dri/intel/intel_reg.h
> b/src/mesa/drivers/dri/intel/intel_reg.h
> index 53b1cb9..737e811 100644
> --- a/src/mesa/drivers/dri/intel/intel_reg.h
> +++ b/src/mesa/drivers/dri/intel/intel_reg.h
> @@ -264,6 +264,9 @@
> #define FENCE_XMAJOR 1
> #define FENCE_YMAJOR 2
>
> +#define _3D_CHICKEN3 0x2090
> +#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
> +
> #define SO_NUM_PRIM_STORAGE_NEEDED 0x2280
> #define SO_PRIM_STORAGE_NEEDED0_IVB 0x5240
> #define SO_PRIM_STORAGE_NEEDED1_IVB 0x5248
> --
> 1.7.11.4
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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