For tracking live variables, we want to know when a register is completely
rewritten, so we need to be able to compare a writemask to the size of the
register. There's also potential use for this in register coalescing.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 +--
src/mesa/drivers/dri/i965/brw_vec4.h | 5 ++-
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 +--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 37 +++++++++++---------
4 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 917959d..47a2d58 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -887,9 +887,9 @@ vec4_visitor::split_virtual_grfs()
if (this->virtual_grf_sizes[i] == 1)
continue;
- new_virtual_grf[i] = virtual_grf_alloc(1);
+ new_virtual_grf[i] = virtual_grf_alloc(1, this->virtual_grf_chans[i]);
for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
- int reg = virtual_grf_alloc(1);
+ int reg = virtual_grf_alloc(1, this->virtual_grf_chans[i]);
assert(reg == new_virtual_grf[i] + j - 1);
(void) reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 12b2ebe..cd05462 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -226,7 +226,10 @@ public:
ir_instruction *base_ir;
const char *current_annotation;
+ /** For each virtual grf, the number of contiguous registers it needs */
int *virtual_grf_sizes;
+ /** For each virtual grf, the number of channels used per register. */
+ int *virtual_grf_chans;
int virtual_grf_count;
int virtual_grf_array_size;
int first_non_payload_grf;
@@ -294,7 +297,7 @@ public:
bool run(void);
void fail(const char *msg, ...);
- int virtual_grf_alloc(int size);
+ int virtual_grf_alloc(int size, int chans);
void setup_uniform_clipplane_values();
int setup_uniform_values(int loc, const glsl_type *type);
void setup_builtin_uniform_values(ir_variable *ir);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index bad2728..5529794 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -330,7 +330,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
src_reg spill_reg = inst->src[i];
- inst->src[i].reg = virtual_grf_alloc(1);
+ inst->src[i].reg = virtual_grf_alloc(1, 4);
dst_reg temp = dst_reg(inst->src[i]);
/* Only read the necessary channels, to avoid overwriting the rest
@@ -347,7 +347,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
dst_reg spill_reg = inst->dst;
- inst->dst.reg = virtual_grf_alloc(1);
+ inst->dst.reg = virtual_grf_alloc(1, 4);
/* We don't want a swizzle when reading from the source; read the
* whole register and use spill_reg's writemask to select which
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 59428a1..dba999b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -402,7 +402,7 @@ type_size(const struct glsl_type *type)
}
int
-vec4_visitor::virtual_grf_alloc(int size)
+vec4_visitor::virtual_grf_alloc(int size, int chans)
{
if (virtual_grf_array_size <= virtual_grf_count) {
if (virtual_grf_array_size == 0)
@@ -411,12 +411,15 @@ vec4_visitor::virtual_grf_alloc(int size)
virtual_grf_array_size *= 2;
virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
virtual_grf_array_size);
+ virtual_grf_chans = reralloc(mem_ctx, virtual_grf_chans, int,
+ virtual_grf_array_size);
virtual_grf_reg_map = reralloc(mem_ctx, virtual_grf_reg_map, int,
virtual_grf_array_size);
}
virtual_grf_reg_map[virtual_grf_count] = virtual_grf_reg_count;
virtual_grf_reg_count += size;
virtual_grf_sizes[virtual_grf_count] = size;
+ virtual_grf_chans[virtual_grf_count] = chans;
return virtual_grf_count++;
}
@@ -424,15 +427,15 @@ src_reg::src_reg(class vec4_visitor *v, const struct
glsl_type *type)
{
init();
- this->file = GRF;
- this->reg = v->virtual_grf_alloc(type_size(type));
-
- if (type->is_array() || type->is_record()) {
- this->swizzle = BRW_SWIZZLE_NOOP;
- } else {
- this->swizzle = swizzle_for_size(type->vector_elements);
- }
+ int chans;
+ if (type->is_array() || type->is_record())
+ chans = 4;
+ else
+ chans = type->vector_elements;
+ this->file = GRF;
+ this->reg = v->virtual_grf_alloc(type_size(type), chans);
+ this->swizzle = swizzle_for_size(chans);
this->type = brw_type_for_base_type(type);
}
@@ -440,15 +443,15 @@ dst_reg::dst_reg(class vec4_visitor *v, const struct
glsl_type *type)
{
init();
- this->file = GRF;
- this->reg = v->virtual_grf_alloc(type_size(type));
-
- if (type->is_array() || type->is_record()) {
- this->writemask = WRITEMASK_XYZW;
- } else {
- this->writemask = (1 << type->vector_elements) - 1;
- }
+ int chans;
+ if (type->is_array() || type->is_record())
+ chans = 4;
+ else
+ chans = type->vector_elements;
+ this->file = GRF;
+ this->reg = v->virtual_grf_alloc(type_size(type), chans);
+ this->writemask = (1 << chans) - 1;
this->type = brw_type_for_base_type(type);
}
--
1.7.10.4
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