I have skimmed over these and besides my comments for patches 2 and 3,
this series is:
Reviewed-by: Marek Olšák <mar...@gmail.com>
Marek
On Tue, Jul 24, 2012 at 8:36 PM, Tom Stellard <tstel...@gmail.com> wrote:
> ---
> src/gallium/drivers/r600/evergreend.h | 5 -----
> src/gallium/drivers/r600/r600_pipe.h | 18 ++++++++++++++++++
> 2 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreend.h
> b/src/gallium/drivers/r600/evergreend.h
> index 6c4873c..55061d4 100644
> --- a/src/gallium/drivers/r600/evergreend.h
> +++ b/src/gallium/drivers/r600/evergreend.h
> @@ -116,11 +116,6 @@
> #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
> #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) |
> PKT_COUNT_S(count))
>
> -#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
> -
> -/*Evergreen Compute packet3*/
> -#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) |
> PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) |
> RADEON_CP_PACKET3_COMPUTE_MODE)
> -
> /* Registers */
> #define R_0084FC_CP_STRMOUT_CNTL 0x000084FC
> #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
> diff --git a/src/gallium/drivers/r600/r600_pipe.h
> b/src/gallium/drivers/r600/r600_pipe.h
> index 7fdf2f8..222b87b 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -616,6 +616,11 @@ unsigned r600_tex_compare(unsigned compare);
> #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
> #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) |
> PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
>
> +#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
> +
> +/*Evergreen Compute packet3*/
> +#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) |
> PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) |
> RADEON_CP_PACKET3_COMPUTE_MODE)
> +
> static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned
> value)
> {
> cb->buf[cb->atom.num_dw++] = value;
> @@ -745,6 +750,13 @@ static INLINE void r600_write_context_reg_seq(struct
> radeon_winsys_cs *cs, unsig
> cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
> }
>
> +static INLINE void r600_write_compute_context_reg_seq(struct
> radeon_winsys_cs *cs, unsigned reg, unsigned num)
> +{
> + r600_write_context_reg_seq(cs, reg, num);
> + /* Set the compute bit on the packet header */
> + cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
> +}
> +
> static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs,
> unsigned reg, unsigned num)
> {
> assert(reg >= R600_CTL_CONST_OFFSET);
> @@ -765,6 +777,12 @@ static INLINE void r600_write_context_reg(struct
> radeon_winsys_cs *cs, unsigned
> r600_write_value(cs, value);
> }
>
> +static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs
> *cs, unsigned reg, unsigned value)
> +{
> + r600_write_compute_context_reg_seq(cs, reg, 1);
> + r600_write_value(cs, value);
> +}
> +
> static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs,
> unsigned reg, unsigned value)
> {
> r600_write_ctl_const_seq(cs, reg, 1);
> --
> 1.7.7.6
>
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