Signed-off-by: Christian König <deathsim...@vodafone.de>
---
.../drivers/radeonsi/evergreen_hw_context.c | 32 --------------
src/gallium/drivers/radeonsi/evergreen_state.c | 46 --------------------
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 2 -
src/gallium/drivers/radeonsi/si_state.c | 44 +++++++++++++++++++
src/gallium/drivers/radeonsi/si_state.h | 2 +
5 files changed, 46 insertions(+), 80 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c
b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
index 157fe01..299ead8 100644
--- a/src/gallium/drivers/radeonsi/evergreen_hw_context.c
+++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
@@ -51,38 +51,6 @@ static const struct r600_reg si_context_reg_list[] = {
{GROUP_FORCE_NEW_BLOCK, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
{GROUP_FORCE_NEW_BLOCK, 0},
- {R_028644_SPI_PS_INPUT_CNTL_0, 0},
- {R_028648_SPI_PS_INPUT_CNTL_1, 0},
- {R_02864C_SPI_PS_INPUT_CNTL_2, 0},
- {R_028650_SPI_PS_INPUT_CNTL_3, 0},
- {R_028654_SPI_PS_INPUT_CNTL_4, 0},
- {R_028658_SPI_PS_INPUT_CNTL_5, 0},
- {R_02865C_SPI_PS_INPUT_CNTL_6, 0},
- {R_028660_SPI_PS_INPUT_CNTL_7, 0},
- {R_028664_SPI_PS_INPUT_CNTL_8, 0},
- {R_028668_SPI_PS_INPUT_CNTL_9, 0},
- {R_02866C_SPI_PS_INPUT_CNTL_10, 0},
- {R_028670_SPI_PS_INPUT_CNTL_11, 0},
- {R_028674_SPI_PS_INPUT_CNTL_12, 0},
- {R_028678_SPI_PS_INPUT_CNTL_13, 0},
- {R_02867C_SPI_PS_INPUT_CNTL_14, 0},
- {R_028680_SPI_PS_INPUT_CNTL_15, 0},
- {R_028684_SPI_PS_INPUT_CNTL_16, 0},
- {R_028688_SPI_PS_INPUT_CNTL_17, 0},
- {R_02868C_SPI_PS_INPUT_CNTL_18, 0},
- {R_028690_SPI_PS_INPUT_CNTL_19, 0},
- {R_028694_SPI_PS_INPUT_CNTL_20, 0},
- {R_028698_SPI_PS_INPUT_CNTL_21, 0},
- {R_02869C_SPI_PS_INPUT_CNTL_22, 0},
- {R_0286A0_SPI_PS_INPUT_CNTL_23, 0},
- {R_0286A4_SPI_PS_INPUT_CNTL_24, 0},
- {R_0286A8_SPI_PS_INPUT_CNTL_25, 0},
- {R_0286AC_SPI_PS_INPUT_CNTL_26, 0},
- {R_0286B0_SPI_PS_INPUT_CNTL_27, 0},
- {R_0286B4_SPI_PS_INPUT_CNTL_28, 0},
- {R_0286B8_SPI_PS_INPUT_CNTL_29, 0},
- {R_0286BC_SPI_PS_INPUT_CNTL_30, 0},
- {R_0286C0_SPI_PS_INPUT_CNTL_31, 0},
{R_0286C4_SPI_VS_OUT_CONFIG, 0},
{R_0286CC_SPI_PS_INPUT_ENA, 0},
{R_0286D0_SPI_PS_INPUT_ADDR, 0},
diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c
b/src/gallium/drivers/radeonsi/evergreen_state.c
index fdf9047..d336bd8 100644
--- a/src/gallium/drivers/radeonsi/evergreen_state.c
+++ b/src/gallium/drivers/radeonsi/evergreen_state.c
@@ -1288,50 +1288,4 @@ void si_pipe_shader_vs(struct pipe_context *ctx, struct
si_pipe_shader *shader)
NULL, 0);
}
-void si_update_spi_map(struct r600_context *rctx)
-{
- struct r600_shader *ps = &rctx->ps_shader->shader;
- struct r600_shader *vs = &rctx->vs_shader->shader;
- struct r600_pipe_state *rstate = &rctx->spi;
- unsigned i, j, tmp;
-
- rstate->nregs = 0;
-
- for (i = 0; i < ps->ninput; i++) {
- tmp = 0;
-
-#if 0
- /* XXX: Flat shading hangs the GPU */
- if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
- ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
- (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
- rctx->rasterizer && rctx->rasterizer->flatshade)) {
- tmp |= S_028644_FLAT_SHADE(1);
- }
-#endif
-
- if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
- rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
- tmp |= S_028644_PT_SPRITE_TEX(1);
- }
-
- for (j = 0; j < vs->noutput; j++) {
- if (ps->input[i].name == vs->output[j].name &&
- ps->input[i].sid == vs->output[j].sid) {
- tmp |=
S_028644_OFFSET(vs->output[j].param_offset);
- break;
- }
- }
- if (j == vs->noutput) {
- /* No corresponding output found, load defaults into
input */
- tmp |= S_028644_OFFSET(0x20);
- }
-
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 +
i * 4,
- tmp, NULL, 0);
- }
-
- if (rstate->nregs > 0)
- r600_context_pipe_state_set(rctx, rstate);
-}
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 5e39d14..6898cf9 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -210,7 +210,6 @@ struct r600_context {
struct r600_pipe_state vs_const_buffer;
struct r600_pipe_state vs_user_data;
struct r600_pipe_state ps_const_buffer;
- struct r600_pipe_state spi;
struct pipe_query *current_render_cond;
unsigned current_render_cond_mode;
struct pipe_query *saved_render_cond;
@@ -300,7 +299,6 @@ static INLINE void r600_atom_dirty(struct r600_context
*rctx, struct r600_atom *
void cayman_init_state_functions(struct r600_context *rctx);
void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader
*shader);
void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader
*shader);
-void si_update_spi_map(struct r600_context *rctx);
uint32_t si_translate_vertexformat(struct pipe_screen *screen,
enum pipe_format format,
const struct util_format_description *desc,
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index d2dd802..08aa54e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1431,3 +1431,47 @@ bool si_update_draw_info_state(struct r600_context *rctx,
si_pm4_set_state(rctx, draw_info, pm4);
return true;
}
+
+void si_update_spi_map(struct r600_context *rctx)
+{
+ struct r600_shader *ps = &rctx->ps_shader->shader;
+ struct r600_shader *vs = &rctx->vs_shader->shader;
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ unsigned i, j, tmp;
+
+ for (i = 0; i < ps->ninput; i++) {
+ tmp = 0;
+
+#if 0
+ /* XXX: Flat shading hangs the GPU */
+ if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
+ ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
+ (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
+ rctx->rasterizer && rctx->rasterizer->flatshade)) {
+ tmp |= S_028644_FLAT_SHADE(1);
+ }
+#endif
+
+ if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+
+ for (j = 0; j < vs->noutput; j++) {
+ if (ps->input[i].name == vs->output[j].name &&
+ ps->input[i].sid == vs->output[j].sid) {
+ tmp |=
S_028644_OFFSET(vs->output[j].param_offset);
+ break;
+ }
+ }
+
+ if (j == vs->noutput) {
+ /* No corresponding output found, load defaults into
input */
+ tmp |= S_028644_OFFSET(0x20);
+ }
+
+ si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
+ }
+
+ si_pm4_set_state(rctx, spi, pm4);
+}
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 784d4f2..02c1c44 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -75,6 +75,7 @@ union si_state {
struct si_pm4_state *fb_rs;
struct si_pm4_state *fb_blend;
struct si_pm4_state *dsa_stencil_ref;
+ struct si_pm4_state *spi;
struct si_pm4_state *draw_info;
} named;
struct si_pm4_state *array[0];
@@ -111,5 +112,6 @@ void si_init_state_functions(struct r600_context *rctx);
void si_init_config(struct r600_context *rctx);
bool si_update_draw_info_state(struct r600_context *rctx,
const struct pipe_draw_info *info);
+void si_update_spi_map(struct r600_context *rctx);
#endif
--
1.7.9.5
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