To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer. This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.
No functional change, since the CMS layout is not enabled yet.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 9 +++++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 45 ++++++++++++++++++++++++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 14 +++++++
3 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index a801bb7..6530b99 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -282,6 +282,15 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
}
}
+ if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ bool ok = intel_miptree_alloc_mcs(intel, irb->mt, rb->NumSamples);
+ if (!ok) {
+ intel_miptree_release(&irb->mt->hiz_mt);
+ intel_miptree_release(&irb->mt);
+ return false;
+ }
+ }
+
return true;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index f97668a..84fc477 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -406,6 +406,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
intel_region_release(&((*mt)->region));
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->hiz_mt);
+ intel_miptree_release(&(*mt)->mcs_mt);
intel_resolve_map_clear(&(*mt)->hiz_map);
for (i = 0; i < MAX_TEXTURE_LEVELS; i++) {
@@ -637,6 +638,50 @@ intel_miptree_copy_teximage(struct intel_context *intel,
}
bool
+intel_miptree_alloc_mcs(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ GLuint num_samples)
+{
+ assert(mt->mcs_mt == NULL);
+ assert(intel->gen >= 7); /* MCS only used on Gen7+ */
+ assert(num_samples == 4); /* TODO: support 8x MSAA */
+
+ /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
+ *
+ * "The MCS surface must be stored as Tile Y."
+ *
+ * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force
+ * intel_miptree_create() to use Y tiling. msaa_format is otherwise
+ * ignored for the MCS miptree.
+ */
+ mt->mcs_mt = intel_miptree_create(intel,
+ mt->target,
+ MESA_FORMAT_A8,
+ mt->first_level,
+ mt->last_level,
+ mt->width0,
+ mt->height0,
+ mt->depth0,
+ true,
+ 0 /* num_samples */,
+ INTEL_MSAA_LAYOUT_CMS);
+
+ /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
+ *
+ * When MCS buffer is enabled and bound to MSRT, it is required that it
+ * is cleared prior to any rendering.
+ *
+ * Since we don't use the MCS buffer for any purpose other than rendering,
+ * it makes sense to just clear it immediately upon allocation.
+ */
+ void *data = intel_region_map(intel, mt->mcs_mt->region, 0);
+ memset(data, 0, mt->mcs_mt->region->bo->size);
+ intel_region_unmap(intel, mt->mcs_mt->region);
+
+ return mt->mcs_mt;
+}
+
+bool
intel_miptree_alloc_hiz(struct intel_context *intel,
struct intel_mipmap_tree *mt,
GLuint num_samples)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index e0ed4fe..f8245a6 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -272,6 +272,15 @@ struct intel_mipmap_tree
*/
struct intel_mipmap_tree *stencil_mt;
+ /**
+ * \brief MCS miptree for multisampled textures.
+ *
+ * This miptree contains the "multisample control surface", which stores
+ * the necessary information to implement compressed MSAA on Gen7+
+ * (INTEL_MSAA_FORMAT_CMS).
+ */
+ struct intel_mipmap_tree *mcs_mt;
+
/* These are also refcounted:
*/
GLuint refcount;
@@ -384,6 +393,11 @@ intel_miptree_s8z24_gather(struct intel_context *intel,
uint32_t level,
uint32_t layer);
+bool
+intel_miptree_alloc_mcs(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ GLuint num_samples);
+
/**
* \name Miptree HiZ functions
* \{
--
1.7.7.6
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