The mesa process has switched to using merge requests.
The steps for creating a MR are:
1*) Click "fork" in the Meso repo to create a private repo where
you'll push branches for MRs.
2) git push your branch into your private repo
3) The "git push" command printed a link to create a MR for that
branch. Open it.
4*) Add labels, then click "Allow commits from members who can merge
to the target branch" and click Submit.
Merging a branch:
1*) Check that all CI pipelines have succeeded.
2) Rebase your local branch and force-push to your private branch.
3) Wait for the CI to complete
4) Push the merge button
On Fri, Dec 13, 2019 at 4:43 PM Zhang, Boyuan <boyuan.zh...@amd.com> wrote:
>
> Port changes from radeon_vcn_enc_1_2.c to radeon_vcn_enc_2_0.c
>
>
>
> Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
>
> off when rate control is disabled (e.g. constant qp).
>
>
>
> Signed-off-by: Boyuan Zhang <boyuan.zh...@amd.com>
>
> ---
>
> src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c | 8 +++++++-
>
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>
>
> diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
> b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
>
> index d2c6378a055..580a084a1c1 100644
>
> --- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
>
> +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
>
> @@ -196,7 +196,13 @@ static void radeon_enc_nalu_pps_hevc(struct
> radeon_encoder *enc)
>
> radeon_enc_code_se(enc, 0x0);
>
> radeon_enc_code_fixed_bits(enc,
> enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
>
> radeon_enc_code_fixed_bits(enc, 0x0, 1);
>
> - radeon_enc_code_fixed_bits(enc, 0x0, 1);
>
> + if (enc->enc_pic.rc_session_init.rate_control_method ==
>
> + RENCODE_RATE_CONTROL_METHOD_NONE)
>
> + radeon_enc_code_fixed_bits(enc, 0x0, 1);
>
> + else {
>
> + radeon_enc_code_fixed_bits(enc, 0x1, 1);
>
> + radeon_enc_code_ue(enc, 0x0);
>
> + }
>
> radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
>
> radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
>
> radeon_enc_code_fixed_bits(enc, 0x0, 1);
>
> --
>
> 2.17.1
>
>
>
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