On 27/8/19 11:13, Zhaowei Yuan wrote:
Four bytes of src_surf will be compressed into a 32-bits data
and stored into dst_surf, and dst_surf is read as z-order,so
its width must be aligned to multiples of 8(4x2) before devided
by 2.
Signed-off-by: Zhaowei Yuan <zhaowei.y...@samsung.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111266
---
src/gallium/drivers/vc4/vc4_blit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/vc4/vc4_blit.c
b/src/gallium/drivers/vc4/vc4_blit.c
index d3cc515..7697bfa 100644
--- a/src/gallium/drivers/vc4/vc4_blit.c
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -361,6 +361,7 @@ vc4_yuv_blit(struct pipe_context *pctx, const struct
pipe_blit_info *info)
return false;
}
dst_surf->width /= 2;
+ dst_surf->width = align(dst_surf->width, 8) / 2;
The commit message and what you are doing here is somewhat inconsistent,
as you are dividing by two twice. Shouldn't the previous width division
being replaced instead of adding a new aligned one? It is somewhat
confusing to divide by two, and then align and divide by two again.
FWIW, at this point it would be advisable if you send vc4/v3d patches as
gitlab MR, as lately we are using it more that the mesa list.
BR
if (dst->cpp == 1)
dst_surf->height /= 2;
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