Fixes piglits:
        call.cl
        calls-larget-struct.cl
        calls-struct.cl
        calls-workitem-id.cl
        realign-stack.cl
        tail-calls.cl

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
---
The piglit test now pass using llvm-7,8,git.
ImageMagick works on my raven, but some test still fail on
carrizo/iceland.
Other workloads (like shoc) that used function calls also work ok.
ocltoys work after removing static keyword from .cl files.
 src/amd/common/ac_binary.c                | 30 +++++++++++++++++++++++
 src/gallium/drivers/radeonsi/si_compute.c |  6 -----
 2 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 18dc72c61f0..4d152fcf1be 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -178,6 +178,36 @@ bool ac_elf_read(const char *elf_data, unsigned elf_size,
 
        parse_relocs(elf, relocs, symbols, symbol_sh_link, binary);
 
+       // Apply relocations
+       for (int i = 0; i < binary->reloc_count; ++i) {
+               struct ac_shader_reloc *r = &binary->relocs[i];
+               uint32_t *loc = (uint32_t*)(binary->code + r->offset);
+               /* Section target relocations store symbol offsets as
+                * values in reloc location. We're expected to adjust it for
+                * start of the section. However, R_AMDGPU_REL32 are
+                * PC relative relocations, so we need to recompute the
+                * delta between reloc locatin and the target adress.
+                */
+               if (r->target_type == 0x3) { // section relocation
+                       uint32_t target_offset = *loc; // already adjusted
+                       int64_t diff = target_offset - r->offset;
+                       if (r->type == 0xa) { // R_AMDGPU_REL32_LO
+                               // address of the 'lo' instruction is 4B below
+                               // the relocation point, but the target has
+                               // alredy been adjusted.
+                               *loc = (diff & 0xffffffff);
+                       } else if (r->type == 0xb) { // R_AMDGPU_REL32_HI
+                               // 'hi' relocation is 8B above 'lo' relocation
+                               *loc = ((diff - 8) >> 32);
+                       } else {
+                               success = false;
+                               fprintf(stderr, "Unsupported section 
relocation: type: %d, offset: %lx, value: %x\n",
+                                               r->type, r->offset, *loc);
+                       }
+               } else
+                       success = false;
+       }
+
        if (elf){
                elf_end(elf);
        }
diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index b9cea00eeeb..88631369a62 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -246,12 +246,6 @@ static void *si_create_compute_state(
                        const amd_kernel_code_t *code_object =
                                si_compute_get_code_object(program, 0);
                        code_object_to_config(code_object, 
&program->shader.config);
-                       if (program->shader.binary.reloc_count != 0) {
-                               fprintf(stderr, "Error: %d unsupported 
relocations\n",
-                                       program->shader.binary.reloc_count);
-                               FREE(program);
-                               return NULL;
-                       }
                } else {
                        si_shader_binary_read_config(&program->shader.binary,
                                     &program->shader.config, 0);
-- 
2.21.0

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