From: Marek Olšák <marek.ol...@amd.com>
All registers in the array need to be updated if any of them is changed.
Only apps writing gl_ViewportIndex were affected by this bug.
---
src/gallium/drivers/radeonsi/si_blit.c | 2 +-
src/gallium/drivers/radeonsi/si_gfx_cs.c | 3 -
src/gallium/drivers/radeonsi/si_pipe.h | 9 +-
src/gallium/drivers/radeonsi/si_state.c | 8 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 10 +-
.../drivers/radeonsi/si_state_viewport.c | 101 ++++++------------
6 files changed, 40 insertions(+), 93 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 610de289a20..9d3d7d3d27a 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -51,21 +51,21 @@ void si_blitter_begin(struct si_context *sctx, enum
si_blitter_op op)
util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
(struct
pipe_stream_output_target**)sctx->streamout.targets);
util_blitter_save_rasterizer(sctx->blitter,
sctx->queued.named.rasterizer);
if (op & SI_SAVE_FRAGMENT_STATE) {
util_blitter_save_blend(sctx->blitter,
sctx->queued.named.blend);
util_blitter_save_depth_stencil_alpha(sctx->blitter,
sctx->queued.named.dsa);
util_blitter_save_stencil_ref(sctx->blitter,
&sctx->stencil_ref.state);
util_blitter_save_fragment_shader(sctx->blitter,
sctx->ps_shader.cso);
util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
- util_blitter_save_scissor(sctx->blitter,
&sctx->scissors.states[0]);
+ util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
util_blitter_save_window_rectangles(sctx->blitter,
sctx->window_rectangles_include,
sctx->num_window_rectangles,
sctx->window_rectangles);
}
if (op & SI_SAVE_FRAMEBUFFER)
util_blitter_save_framebuffer(sctx->blitter,
&sctx->framebuffer.state);
if (op & SI_SAVE_TEXTURES) {
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c
b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 922fc560d74..780ee3b558f 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -315,23 +315,20 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
if (ctx->chip_class >= GFX9)
si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
/* CLEAR_STATE disables all window rectangles. */
if (!has_clear_state || ctx->num_window_rectangles > 0)
si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
- ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
- ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
- ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
if (ctx->scratch_buffer) {
si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
}
if (ctx->streamout.suspended) {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index a4c90a4f69f..d8a32e4d542 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -662,28 +662,21 @@ enum si_quant_mode {
};
struct si_signed_scissor {
int minx;
int miny;
int maxx;
int maxy;
enum si_quant_mode quant_mode;
};
-struct si_scissors {
- unsigned dirty_mask;
- struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
-};
-
struct si_viewports {
- unsigned dirty_mask;
- unsigned depth_range_dirty_mask;
struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
};
struct si_clip_state {
struct pipe_clip_state state;
bool any_nonzeros;
};
struct si_streamout_target {
@@ -873,21 +866,21 @@ struct si_context {
/* Atom declarations. */
struct si_framebuffer framebuffer;
unsigned sample_locs_num_samples;
uint16_t sample_mask;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct si_clip_state clip_state;
struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
- struct si_scissors scissors;
+ struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
struct si_streamout streamout;
struct si_viewports viewports;
unsigned num_window_rectangles;
bool window_rectangles_include;
struct pipe_scissor_state window_rectangles[4];
/* Precomputed states. */
struct si_pm4_state *init_config;
struct si_pm4_state *init_config_gs_rings;
bool init_config_has_vgt_flush;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index bc7e777ad73..2266b0a0824 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1008,36 +1008,32 @@ static void si_bind_rs_state(struct pipe_context *ctx,
void *state)
si_mark_atom_dirty(sctx,
&sctx->atoms.s.msaa_sample_locs);
}
sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
sctx->current_vs_state |=
S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
si_pm4_bind_state(sctx, rasterizer, rs);
si_update_poly_offset_state(sctx);
if (!old_rs ||
- old_rs->scissor_enable != rs->scissor_enable) {
- sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ old_rs->scissor_enable != rs->scissor_enable)
si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
- }
if (!old_rs ||
old_rs->line_width != rs->line_width ||
old_rs->max_point_size != rs->max_point_size ||
old_rs->half_pixel_center != rs->half_pixel_center)
si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
if (!old_rs ||
- old_rs->clip_halfz != rs->clip_halfz) {
- sctx->viewports.depth_range_dirty_mask = (1 <<
SI_MAX_VIEWPORTS) - 1;
+ old_rs->clip_halfz != rs->clip_halfz)
si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
- }
if (!old_rs ||
old_rs->clip_plane_enable != rs->clip_plane_enable ||
old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
rs->line_stipple_enable;
if (!old_rs ||
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8798f9ad0a0..e65223ccf74 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1487,24 +1487,23 @@ static void si_draw_vbo(struct pipe_context *ctx, const
struct pipe_draw_info *i
/* Emit all states except possibly render condition. */
si_emit_all_states(sctx, info, masked_atoms);
si_emit_cache_flush(sctx);
/* <-- CUs are idle here. */
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
sctx->atoms.s.render_cond.emit(sctx);
if (has_gfx9_scissor_bug &&
(sctx->context_roll ||
- si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
- sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
sctx->atoms.s.scissors.emit(sctx);
- }
+
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size,
index_offset);
/* <-- CUs are busy here. */
/* Start prefetches after the draw has been started. Both will
run
* in parallel, but starting the draw first is more important.
*/
if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
cik_emit_prefetch_L2(sctx, false);
@@ -1519,24 +1518,23 @@ static void si_draw_vbo(struct pipe_context *ctx, const
struct pipe_draw_info *i
if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
cik_emit_prefetch_L2(sctx, true);
if (!si_upload_graphics_shader_descriptors(sctx))
return;
si_emit_all_states(sctx, info, masked_atoms);
if (has_gfx9_scissor_bug &&
(sctx->context_roll ||
- si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
- sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
sctx->atoms.s.scissors.emit(sctx);
- }
+
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size,
index_offset);
/* Prefetch the remaining shaders after the draw has been
* started. */
if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
cik_emit_prefetch_L2(sctx, false);
}
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 6f348a9b58d..792d1c4efd1 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -30,27 +30,26 @@
static void si_set_scissor_states(struct pipe_context *pctx,
unsigned start_slot,
unsigned num_scissors,
const struct pipe_scissor_state *state)
{
struct si_context *ctx = (struct si_context *)pctx;
int i;
for (i = 0; i < num_scissors; i++)
- ctx->scissors.states[start_slot + i] = state[i];
+ ctx->scissors[start_slot + i] = state[i];
if (!ctx->queued.named.rasterizer ||
!ctx->queued.named.rasterizer->scissor_enable)
return;
- ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
}
/* Since the guard band disables clipping, we have to clip per-pixel
* using a scissor.
*/
static void si_get_scissor_from_viewport(struct si_context *ctx,
const struct pipe_viewport_state *vp,
struct si_signed_scissor *scissor)
{
@@ -282,59 +281,49 @@ static void si_emit_guardband(struct si_context *ctx)
S_028BE4_PIX_CENTER(rs->half_pixel_center) |
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
vp_as_scissor.quant_mode));
if (initial_cdw != ctx->gfx_cs->current.cdw)
ctx->context_roll = true;
}
static void si_emit_scissors(struct si_context *ctx)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
- struct pipe_scissor_state *states = ctx->scissors.states;
- unsigned mask = ctx->scissors.dirty_mask;
+ struct pipe_scissor_state *states = ctx->scissors;
bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
- if (!(mask & 1))
- return;
-
radeon_set_context_reg_seq(cs,
R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] :
NULL);
- ctx->scissors.dirty_mask &= ~1; /* clear one bit */
return;
}
- while (mask) {
- int start, count, i;
-
- u_bit_scan_consecutive_range(&mask, &start, &count);
-
- radeon_set_context_reg_seq(cs,
R_028250_PA_SC_VPORT_SCISSOR_0_TL +
- start * 4 * 2, count * 2);
- for (i = start; i < start+count; i++) {
- si_emit_one_scissor(ctx, cs,
&ctx->viewports.as_scissor[i],
- scissor_enabled ? &states[i] :
NULL);
- }
+ /* All registers in the array need to be updated if any of them is
changed.
+ * This is a hardware requirement.
+ */
+ radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
+ SI_MAX_VIEWPORTS * 2);
+ for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
+ si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
+ scissor_enabled ? &states[i] : NULL);
}
- ctx->scissors.dirty_mask = 0;
}
static void si_set_viewport_states(struct pipe_context *pctx,
unsigned start_slot,
unsigned num_viewports,
const struct pipe_viewport_state *state)
{
struct si_context *ctx = (struct si_context *)pctx;
- unsigned mask;
int i;
for (i = 0; i < num_viewports; i++) {
unsigned index = start_slot + i;
struct si_signed_scissor *scissor =
&ctx->viewports.as_scissor[index];
ctx->viewports.states[index] = state[i];
si_get_scissor_from_viewport(ctx, &state[i], scissor);
@@ -385,24 +374,20 @@ static void si_set_viewport_states(struct pipe_context
*pctx,
*/
if (max_extent <= 1024 && max_corner < 4096) /* 4K scanline
area for guardband */
scissor->quant_mode =
SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
else if (max_extent <= 4096) /* 16K scanline area for guardband
*/
scissor->quant_mode =
SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
else /* 64K scanline area for guardband */
scissor->quant_mode =
SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
}
- mask = ((1 << num_viewports) - 1) << start_slot;
- ctx->viewports.dirty_mask |= mask;
- ctx->viewports.depth_range_dirty_mask |= mask;
- ctx->scissors.dirty_mask |= mask;
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
}
static void si_emit_one_viewport(struct si_context *ctx,
struct pipe_viewport_state *state)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
@@ -411,97 +396,79 @@ static void si_emit_one_viewport(struct si_context *ctx,
radeon_emit(cs, fui(state->scale[1]));
radeon_emit(cs, fui(state->translate[1]));
radeon_emit(cs, fui(state->scale[2]));
radeon_emit(cs, fui(state->translate[2]));
}
static void si_emit_viewports(struct si_context *ctx)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
struct pipe_viewport_state *states = ctx->viewports.states;
- unsigned mask = ctx->viewports.dirty_mask;
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
- if (!(mask & 1))
- return;
-
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
si_emit_one_viewport(ctx, &states[0]);
- ctx->viewports.dirty_mask &= ~1; /* clear one bit */
return;
}
- while (mask) {
- int start, count, i;
-
- u_bit_scan_consecutive_range(&mask, &start, &count);
-
- radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
- start * 4 * 6, count * 6);
- for (i = start; i < start+count; i++)
- si_emit_one_viewport(ctx, &states[i]);
- }
- ctx->viewports.dirty_mask = 0;
+ /* All registers in the array need to be updated if any of them is
changed.
+ * This is a hardware requirement.
+ */
+ radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
+ 0, SI_MAX_VIEWPORTS * 6);
+ for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++)
+ si_emit_one_viewport(ctx, &states[i]);
}
static inline void
si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
bool window_space_position, float *zmin, float *zmax)
{
if (window_space_position) {
*zmin = 0;
*zmax = 1;
return;
}
util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
}
static void si_emit_depth_ranges(struct si_context *ctx)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
struct pipe_viewport_state *states = ctx->viewports.states;
- unsigned mask = ctx->viewports.depth_range_dirty_mask;
bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
bool window_space = ctx->vs_disables_clipping_viewport;
float zmin, zmax;
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
- if (!(mask & 1))
- return;
-
si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
&zmin, &zmax);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
- ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
return;
}
- while (mask) {
- int start, count, i;
-
- u_bit_scan_consecutive_range(&mask, &start, &count);
-
- radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
- start * 4 * 2, count * 2);
- for (i = start; i < start+count; i++) {
- si_viewport_zmin_zmax(&states[i], clip_halfz,
window_space,
- &zmin, &zmax);
- radeon_emit(cs, fui(zmin));
- radeon_emit(cs, fui(zmax));
- }
+ /* All registers in the array need to be updated if any of them is
changed.
+ * This is a hardware requirement.
+ */
+ radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0,
+ SI_MAX_VIEWPORTS * 2);
+ for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
+ si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
+ &zmin, &zmax);
+ radeon_emit(cs, fui(zmin));
+ radeon_emit(cs, fui(zmax));
}
- ctx->viewports.depth_range_dirty_mask = 0;
}
static void si_emit_viewport_states(struct si_context *ctx)
{
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);
}
/**
* This reacts to 2 state changes:
@@ -520,43 +487,39 @@ void si_update_vs_viewport_state(struct si_context *ctx)
if (!info)
return;
/* When the VS disables clipping and viewport transformation. */
vs_window_space =
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
ctx->vs_disables_clipping_viewport = vs_window_space;
- ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
- ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS)
- 1;
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
}
/* Viewport index handling. */
if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
return;
/* This changes how the guardband is computed. */
ctx->vs_writes_viewport_index = info->writes_viewport_index;
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
- if (!ctx->vs_writes_viewport_index)
- return;
-
- if (ctx->scissors.dirty_mask)
+ /* Emit scissors and viewports that were enabled by having
+ * the ViewportIndex output.
+ */
+ if (info->writes_viewport_index) {
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
-
- if (ctx->viewports.dirty_mask ||
- ctx->viewports.depth_range_dirty_mask)
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
+ }
}
static void si_emit_window_rectangles(struct si_context *sctx)
{
/* There are four clipping rectangles. Their corner coordinates are
inclusive.
* Every pixel is assigned a number from 0 and 15 by setting bits 0-3
depending
* on whether the pixel is inside cliprects 0-3, respectively. For
example,
* if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is
assigned
* the number 3 (binary 0011).
*
--
2.17.1
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