vindex is always 0.
v3: use the raw version
v2: do not force enable IDXEN when unecessary
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/common/ac_llvm_build.c | 20 ++++++++++++++++++++
src/amd/common/ac_llvm_build.h | 9 +++++++++
src/amd/common/ac_nir_to_llvm.c | 25 ++++---------------------
3 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 99fb1ecc327..c86a4f98864 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1741,6 +1741,26 @@ ac_build_raw_tbuffer_store(struct ac_llvm_context *ctx,
writeonly_memory, false);
}
+void
+ac_build_tbuffer_store_short(struct ac_llvm_context *ctx,
+ LLVMValueRef rsrc,
+ LLVMValueRef vdata,
+ LLVMValueRef voffset,
+ LLVMValueRef soffset,
+ bool glc,
+ bool writeonly_memory)
+{
+ unsigned dfmt = V_008F0C_BUF_DATA_FORMAT_16;
+ unsigned nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
+
+ vdata = LLVMBuildBitCast(ctx->builder, vdata, ctx->i16, "");
+ vdata = LLVMBuildZExt(ctx->builder, vdata, ctx->i32, "");
+
+ ac_build_raw_tbuffer_store(ctx, rsrc, vdata, voffset, soffset,
+ ctx->i32_0, 1, dfmt, nfmt, glc, false,
+ writeonly_memory);
+}
+
/**
* Set range metadata on an instruction. This can only be used on load and
* call instructions. If you know an instruction can only produce the values
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index ae0bdbcfd1c..723aec53cbe 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -343,6 +343,15 @@ ac_build_raw_tbuffer_load(struct ac_llvm_context *ctx,
bool slc,
bool can_speculate);
+void
+ac_build_tbuffer_store_short(struct ac_llvm_context *ctx,
+ LLVMValueRef rsrc,
+ LLVMValueRef vdata,
+ LLVMValueRef voffset,
+ LLVMValueRef soffset,
+ bool glc,
+ bool writeonly_memory);
+
void
ac_build_struct_tbuffer_store(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5aad5807bb5..7a03e9c15b2 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1521,14 +1521,12 @@ static unsigned get_cache_policy(struct ac_nir_context
*ctx,
static void visit_store_ssbo(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
- const char *store_name;
LLVMValueRef src_data = get_src(ctx, instr->src[0]);
int elem_size_bytes = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data))
/ 8;
unsigned writemask = nir_intrinsic_write_mask(instr);
enum gl_access_qualifier access = nir_intrinsic_access(instr);
bool writeonly_memory = access & ACCESS_NON_READABLE;
unsigned cache_policy = get_cache_policy(ctx, access, false,
writeonly_memory);
- LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true :
ctx->ac.i1false;
LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
get_src(ctx, instr->src[1]), true);
@@ -1571,25 +1569,10 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
LLVMConstInt(ctx->ac.i32, start *
elem_size_bytes, false), "");
if (num_bytes == 2) {
- store_name = "llvm.amdgcn.tbuffer.store.i32";
- data_type = ctx->ac.i32;
- data = LLVMBuildBitCast(ctx->ac.builder, data,
ctx->ac.i16, "");
- data = LLVMBuildZExt(ctx->ac.builder, data, data_type,
"");
- LLVMValueRef tbuffer_params[] = {
- data,
- rsrc,
- ctx->ac.i32_0, /* vindex */
- offset, /* voffset */
- ctx->ac.i32_0,
- ctx->ac.i32_0,
- LLVMConstInt(ctx->ac.i32, 2, false), // dfmt (=
16bit)
- LLVMConstInt(ctx->ac.i32, 4, false), // nfmt (=
uint)
- glc,
- ctx->ac.i1false,
- };
- ac_build_intrinsic(&ctx->ac, store_name,
- ctx->ac.voidt, tbuffer_params, 10,
-
ac_get_store_intr_attribs(writeonly_memory));
+ ac_build_tbuffer_store_short(&ctx->ac, rsrc, data,
+ offset, ctx->ac.i32_0,
+ cache_policy & ac_glc,
+ writeonly_memory);
} else {
int num_channels = num_bytes / 4;
--
2.21.0
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