NIR can produce IR that looks like this:
vec1 1 ssa_51 = ilt ssa_32, ssa_50
vec4 32 ssa_54 = intrinsic load_deref (ssa_53) (0)
vec4 32 ssa_57 = intrinsic load_deref (ssa_56) (0)
vec4 32 ssa_61 = bcsel ssa_51.xxxx, ssa_54, ssa_57
The swizzle on the first bcsel src causes a crash in llvm as it
doesn't seem to expect it. Here we add a special case for the
first bcsel src.
---
src/amd/common/ac_nir_to_llvm.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5fb5c8da609..cebf248427c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -154,13 +154,18 @@ static LLVMBasicBlockRef get_block(struct ac_nir_context
*nir,
static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
nir_alu_src src,
- unsigned num_components)
+ unsigned num_components,
+ bool is_first_bcsel_src)
{
LLVMValueRef value = get_src(ctx, src.src);
bool need_swizzle = false;
assert(value);
unsigned src_components = ac_get_llvm_num_components(value);
+
+ if (is_first_bcsel_src)
+ num_components = 1;
+
for (unsigned i = 0; i < num_components; ++i) {
assert(src.swizzle[i] < src_components);
if (src.swizzle[i] != i)
@@ -584,8 +589,10 @@ static void visit_alu(struct ac_nir_context *ctx, const
nir_alu_instr *instr)
src_components = num_components;
break;
}
- for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
- src[i] = get_alu_src(ctx, instr->src[i], src_components);
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
+ src[i] = get_alu_src(ctx, instr->src[i], src_components,
+ (instr->op == nir_op_b32csel && i == 0));
+ }
switch (instr->op) {
case nir_op_fmov:
--
2.20.1
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