Re: [Mesa-dev] [PATCH v2 26/53] intel/compiler: Extended Math is limited to SIMD8 on half-float

[Pohjolainen, Topi]

On Wed, Dec 19, 2018 at 12:50:54PM +0100, Iago Toral Quiroga wrote:
> From the Skylake PRM, Extended Math Function:
> 
>   "The execution size must be no more than 8 when half-floats
>    are used in source or destination operand."
> 
> Earlier generations do not support Extended Math with half-float.
> 
> v2
>  - Rewrite the code to make it more readable (Jason).
> 
> Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> (v1)
> ---
>  src/intel/compiler/brw_fs.cpp | 29 ++++++++++++++++++++---------
>  1 file changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 3125e5feb1d..933b0b6ffc4 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -5406,18 +5406,29 @@ get_lowered_simd_width(const struct gen_device_info 
> *devinfo,
>     case SHADER_OPCODE_EXP2:
>     case SHADER_OPCODE_LOG2:
>     case SHADER_OPCODE_SIN:
> -   case SHADER_OPCODE_COS:
> +   case SHADER_OPCODE_COS: {
>        /* Unary extended math instructions are limited to SIMD8 on Gen4 and
> -       * Gen6.
> +       * Gen6. Extended Math Function is limited to SIMD8 with half-float.
>         */
> -      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
> -              devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, 
> inst->exec_size) :
> -              MIN2(8, inst->exec_size));
> +      if (devinfo->gen == 6 || (devinfo->gen == 4 && !devinfo->is_g4x))
> +         return MIN2(8, inst->exec_size);
> +      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> +         return MIN2(8, inst->exec_size);
> +      else
> +         return MIN2(16, inst->exec_size);

I was expecting either of these two:


         if ()
            return
         else if ()
            return
         else
            return


or


         if ()
            return

         if ()
            return

         return

> +   }
>  
> -   case SHADER_OPCODE_POW:
> -      /* SIMD16 is only allowed on Gen7+. */
> -      return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
> -              MIN2(8, inst->exec_size));
> +   case SHADER_OPCODE_POW: {
> +      /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
> +       * to SIMD8 with half-float
> +       */
> +      if (devinfo->gen < 7)
> +         return MIN2(8, inst->exec_size);
> +      if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> +         return MIN2(8, inst->exec_size);
> +      else
> +         return MIN2(16, inst->exec_size);
> +   }
>  
>     case SHADER_OPCODE_INT_QUOTIENT:
>     case SHADER_OPCODE_INT_REMAINDER:
> -- 
> 2.17.1
> 
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