On 05/02/2012 02:48 PM, Paul Berry wrote: > When rendering to a miplevel other than 0 within a color, depth, > stencil, or HiZ buffer, we need to tell the GPU to render to an offset > within the buffer, so that the data is written into the correct > miplevel. We do this using a coarse offset (in pages), and a fine > adjustment (the so-called "tile_x" and "tile_y" values, which are > measured in pixels). > > We have always computed the coarse offset and fine adjustment using > intel_renderbuffer_tile_offsets() function. This worked fine for > color and combined depth/stencil buffers, but failed to work properly > when HiZ and separate stencil were in use. It failed to work because > there is only one set of fine adjustment controls shared by the HiZ, > depth, and stencil buffers, so we need to choose tile_x and tile_y > values that are compatible with the tiling of all three buffers, and > then compute separate coarse offsets for each buffer. > > This patch fixes the HiZ and separate stencil case by replacing the > call to intel_renderbuffer_tile_offsets() with calls to two functions: > intel_region_get_tile_masks(), which determines how much of the > adjustment can be performed using offsets and how much can be > performed using tile_x and tile_y, and > intel_region_get_aligned_offset(), which computes the coarse offset. > > intel_region_get_tile_offsets() is still used for color renderbuffers, > so to avoid code duplication, I've re-worked it to use > intel_region_get_tile_masks() and intel_region_get_aligned_offset(). > > On i965 Gen6, fixes piglit tests > "texturing/depthstencil-render-miplevels 1024 X" where X is one of > (depth, depth_and_stencil, depth_stencil_single_binding, depth_x, > depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x). > > On i965 Gen7, the variants of > "texturing/depthstencil-render-miplevels" that contain a stencil > buffer still fail, due to another problem: Gen7 seems to ignore the 3 > LSB's of the tile_y adjustment (and possibly also tile_x). > > v2: Removed spurious comments. Added assertions to check > preconditions of intel_region_get_aligned_offset(). > --- > src/mesa/drivers/dri/i965/brw_misc_state.c | 96 ++++++++++++++++++++++++-- > src/mesa/drivers/dri/i965/gen6_hiz.c | 54 +++++++++++---- > src/mesa/drivers/dri/i965/gen7_hiz.c | 54 +++++++++++---- > src/mesa/drivers/dri/i965/gen7_misc_state.c | 79 ++++++++++++++++++++-- > src/mesa/drivers/dri/intel/intel_fbo.c | 27 ++----- > src/mesa/drivers/dri/intel/intel_fbo.h | 5 ++ > src/mesa/drivers/dri/intel/intel_regions.c | 56 ++++++++++++++++ > src/mesa/drivers/dri/intel/intel_regions.h | 8 ++ > 8 files changed, 319 insertions(+), 60 deletions(-)
Thanks for adding the precondition checks. Reviewed-by: Chad Versace <chad.vers...@linux.intel.com> _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
