When RepCtrl is set, the swizzle field is ignored by the hardware. In
order to ensure a 1-to-1 correspondence between the human-readable
disassembly and the binary instruction encoding always set the swizzle
to XXXX (all zeros) when it is unused due to RepCtrl
Signed-off-by: Sagar Ghuge <sagar.gh...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
---
src/intel/compiler/brw_eu_emit.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 4630b83b1a..483037345e 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -833,7 +833,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \
struct brw_reg src0, \
struct brw_reg src1, \
struct brw_reg src2) \
-{ \
+{ \
+ if (p->current->access_mode == BRW_ALIGN_16) { \
+ if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
+ src0.swizzle = BRW_SWIZZLE_XXXX; \
+ if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
+ src1.swizzle = BRW_SWIZZLE_XXXX; \
+ if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
+ src2.swizzle = BRW_SWIZZLE_XXXX; \
+ } \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
@@ -854,6 +862,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \
assert(src0.type == BRW_REGISTER_TYPE_DF); \
assert(src1.type == BRW_REGISTER_TYPE_DF); \
assert(src2.type == BRW_REGISTER_TYPE_DF); \
+ } \
+ \
+ if (p->current->access_mode == BRW_ALIGN_16) { \
+ if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
+ src0.swizzle = BRW_SWIZZLE_XXXX; \
+ if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
+ src1.swizzle = BRW_SWIZZLE_XXXX; \
+ if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
+ src2.swizzle = BRW_SWIZZLE_XXXX; \
} \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
--
2.17.1
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