This series is partly a re-send of my SHADER_OPCODE_SEND series and partially a new series to enable SENDS support on gen9 and above. The first 11 patches introduce a new SHADER_OPCODE_SEND which is a generic send instruction and lower several of our logical opcodes to it. Not everything is lowered just yet but most of the important stuff is, at least on 7+: texturing, UBO pulls, SSBOs, and images. We can't convert everything to it because certain messages such as spills will likely need magic opcodes for some time. Also, I didn't lower anything on gen4-6 because I really didn't want to spend time fixing it. At some point, we should lower FB writes but that will take a tiny bit more plumbing than we have today.
The second half of the series enables the new split send instructions on Skylake and above. Most of the work is just refactoring and adding helpers here and there. The last patch in the series enables SENDS for surface writes on gen9+ so all SSBO and image access now goes through SENDS. We should also consider splitting texture and FB write payloads at some point in the future but it's much less clear how we want to split those. Another obvious for split messages would be spills where we currently have to copy the offset and the data together where a split message would let us just write the offset to a register and send. I'm leaving that for a rainy day as well. The real primary motivation behind this is that SENDS is required for bindless sampler messages. It's not because of split payloads but because of the extended message descriptor which is where you have to put the 20-bit bindless handle. I would like to start experimenting with using Bindless in Vulkan so the first step along that path is SENDS. Cc: Matt Turner <matts...@gmail.com> Cc: Francisco Jerez <curroje...@riseup.net> Cc: Kenneth Graunke <kenn...@whitecape.org> Jason Ekstrand (21): intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf() intel/fs: Take an explicit exec size in brw_surface_payload_size() intel/eu: Add has_simd4x2 bools to surface_write functions intel/eu: Rework surface descriptor helpers intel/fs: Add a generic SEND opcode intel/fs: Use the generic SEND opcode for surface messages intel/fs: Mark texture surfaces used in brw_fs_nir intel/fs: Use a logical opcode for IMAGE_SIZE intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+ intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+ intel/eu: Use GET_BITS in brw_inst_set_send_ex_desc intel/eu/validate: SEND restrictions also apply to SENDC intel/eu: Add more message descriptor helpers intel/disasm: Rework SEND decoding to use descriptors intel/inst: Fix the ia16_addr_imm helpers intel/inst: Indent some code intel/eu: Add support for the SENDS[C] messages intel/disasm: Properly disassemble split sends intel/fs: Support SENDS in SHADER_OPCODE_SEND intel/fs: Use split sends for surface writes on gen9+ src/intel/compiler/brw_disasm.c | 236 ++++- src/intel/compiler/brw_eu.h | 480 +++++++++- src/intel/compiler/brw_eu_defines.h | 13 +- src/intel/compiler/brw_eu_emit.c | 874 ++++++++---------- src/intel/compiler/brw_eu_validate.c | 64 +- src/intel/compiler/brw_fs.cpp | 467 ++++++++-- src/intel/compiler/brw_fs.h | 13 +- src/intel/compiler/brw_fs_builder.h | 15 + src/intel/compiler/brw_fs_cse.cpp | 6 +- src/intel/compiler/brw_fs_generator.cpp | 341 ++----- src/intel/compiler/brw_fs_nir.cpp | 30 +- src/intel/compiler/brw_fs_reg_allocate.cpp | 6 +- src/intel/compiler/brw_inst.h | 66 +- .../compiler/brw_schedule_instructions.cpp | 90 +- src/intel/compiler/brw_shader.cpp | 10 +- src/intel/compiler/brw_shader.h | 5 + src/mesa/drivers/dri/i965/brw_defines.h | 2 +- 17 files changed, 1720 insertions(+), 998 deletions(-) -- 2.19.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
