Hey Emil, I just pushed v5 upstream. Let me spin a cleanup patch and send that to the ML.
Rob. On 2018-11-16 14:03, Emil Velikov wrote:
Hi Rob, I've spotted a couple of nitpicks, but I don't feel too strongly either way. On Thu, 15 Nov 2018 at 13:28, Robert Foss <robert.f...@collabora.com> wrote: <snip>case PIPE_CAP_VIDEO_MEMORY: return 0; case PIPE_CAP_NATIVE_FENCE_FD: - return 0; + return !!vscreen->vws->supports_fences;Do we need the !! here? AFAICT it's usually done to convert int to bool. <snip>qdws->base.cs_create_fence = virgl_cs_create_fence; qdws->base.fence_wait = virgl_fence_wait; qdws->base.fence_reference = virgl_fence_reference; + qdws->base.fence_server_sync = virgl_fence_server_sync; + qdws->base.fence_get_fd = virgl_fence_get_fd; + qdws->base.supports_fences = drm_version >= VIRGL_DRM_VERSION_FENCE_FD; qdws->base.get_caps = virgl_drm_get_caps; +Unneeded whitespace changes.uint32_t value = 0; getparam.param = VIRTGPU_PARAM_CAPSET_QUERY_FIX; getparam.value = (uint64_t)(uintptr_t)&value;<snip>struct virgl_drm_winsys { struct virgl_winsys base; int fd; + int drm_version;Never assigned? I'd assign it or drop it. <snip>vtws->base.cs_create_fence = virgl_cs_create_fence; vtws->base.fence_wait = virgl_fence_wait; vtws->base.fence_reference = virgl_fence_reference; + vtws->base.supports_fences = 0; vtws->base.flush_frontbuffer = virgl_vtest_flush_frontbuffer; +Unneeded whitespace changes.return &vtws->base; }HTH Emil
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