This is just a small cleanup.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 11 +++++------
src/amd/vulkan/radv_image.c | 2 +-
src/amd/vulkan/radv_meta_clear.c | 4 ++--
src/amd/vulkan/radv_meta_fast_clear.c | 4 ++--
src/amd/vulkan/radv_private.h | 8 ++++----
5 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8e0ed284d6..9fcef5a62d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1344,13 +1344,12 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer,
* cmask eliminate is required.
*/
void
-radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
- bool value)
+radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, bool value)
{
uint64_t pred_val = value;
uint64_t va = radv_buffer_get_va(image->bo);
- va += image->offset + image->dcc_pred_offset;
+ va += image->offset + image->fce_pred_offset;
assert(radv_image_has_dcc(image));
@@ -4333,8 +4332,8 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
radv_initialize_dcc(cmd_buffer, image, value);
- radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
- need_decompress_pass);
+ radv_update_fce_metadata(cmd_buffer, image,
+ need_decompress_pass);
}
if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 64346aa340..7492bf48b5 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -857,7 +857,7 @@ radv_image_alloc_dcc(struct radv_image *image)
image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
/* + 16 for storing the clear values + dcc pred */
image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
- image->dcc_pred_offset = image->clear_value_offset + 8;
+ image->fce_pred_offset = image->clear_value_offset + 8;
image->size = image->dcc_offset + image->surface.dcc_size + 16;
image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
}
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index c8a7f80d55..565dbe4e23 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1158,8 +1158,8 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
flush_bits |= radv_clear_dcc(cmd_buffer, iview->image,
reset_value);
- radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
- need_decompress_pass);
+ radv_update_fce_metadata(cmd_buffer, iview->image,
+ need_decompress_pass);
} else {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
cmask_clear_value);
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 9544ee94f5..27b82339e4 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -586,7 +586,7 @@ radv_emit_set_predication_state_from_image(struct
radv_cmd_buffer *cmd_buffer,
if (value) {
va = radv_buffer_get_va(image->bo) + image->offset;
- va += image->dcc_pred_offset;
+ va += image->fce_pred_offset;
}
si_emit_set_predication_state(cmd_buffer, true, va);
@@ -705,7 +705,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer
*cmd_buffer,
/* Clear the image's fast-clear eliminate predicate because
* FMASK and DCC also imply a fast-clear eliminate.
*/
- radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
+ radv_update_fce_metadata(cmd_buffer, image, false);
if (cmd_buffer->state.predication_type != -1) {
/* Restore previous conditional rendering user state. */
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1628be1002..24e922da5e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1197,9 +1197,9 @@ void radv_update_color_clear_metadata(struct
radv_cmd_buffer *cmd_buffer,
int cb_idx,
uint32_t color_values[2]);
-void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
- bool value);
+void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, bool value);
+
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
@@ -1495,7 +1495,7 @@ struct radv_image {
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint64_t clear_value_offset;
- uint64_t dcc_pred_offset;
+ uint64_t fce_pred_offset;
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
--
2.19.1
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