Signed-off-by: Karol Herbst <kher...@redhat.com>
---
src/amd/vulkan/radv_meta_buffer.c | 8 ++--
src/amd/vulkan/radv_meta_bufimage.c | 16 ++++----
src/amd/vulkan/radv_meta_fast_clear.c | 4 +-
src/amd/vulkan/radv_meta_resolve_cs.c | 4 +-
src/amd/vulkan/radv_query.c | 8 ++--
src/compiler/nir/nir_builder_opcodes_h.py | 15 ++++++-
src/compiler/nir/nir_intrinsics.py | 10 ++---
src/compiler/nir/nir_lower_system_values.c | 40 ++++++++++++-------
src/gallium/auxiliary/nir/tgsi_to_nir.c | 2 +-
src/gallium/drivers/vc4/vc4_nir_lower_blend.c | 4 +-
src/intel/compiler/brw_nir.c | 2 +-
11 files changed, 67 insertions(+), 46 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_buffer.c
b/src/amd/vulkan/radv_meta_buffer.c
index 76854d7bbad..208988c3775 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -15,8 +15,8 @@ build_buffer_fill_shader(struct radv_device *dev)
b.shader->info.cs.local_size[1] = 1;
b.shader->info.cs.local_size[2] = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
@@ -67,8 +67,8 @@ build_buffer_copy_shader(struct radv_device *dev)
b.shader->info.cs.local_size[1] = 1;
b.shader->info.cs.local_size[2] = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
diff --git a/src/amd/vulkan/radv_meta_bufimage.c
b/src/amd/vulkan/radv_meta_bufimage.c
index f5b68f6c9a6..e79919a984b 100644
--- a/src/amd/vulkan/radv_meta_bufimage.c
+++ b/src/amd/vulkan/radv_meta_bufimage.c
@@ -60,8 +60,8 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool
is_3d)
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
@@ -289,8 +289,8 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool
is_3d)
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
@@ -719,8 +719,8 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool
is_3d)
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
@@ -1139,8 +1139,8 @@ build_nir_cleari_compute_shader(struct radv_device *dev,
bool is_3d)
output_img->data.descriptor_set = 0;
output_img->data.binding = 0;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 53f1b31a990..619895c26f9 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -58,8 +58,8 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index e56df7f8a59..1ee8ce32ac0 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -99,8 +99,8 @@ build_resolve_compute_shader(struct radv_device *dev, bool
is_integer, bool is_s
img_type, "out_img");
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 550abe307a1..3dd3390d14e 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -153,8 +153,8 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
nir_builder_instr_insert(&b, &src_buf->instr);
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
@@ -343,8 +343,8 @@ build_pipeline_statistics_query_shader(struct radv_device
*device) {
nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
nir_builder_instr_insert(&b, &src_buf->instr);
- nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
- nir_ssa_def *wg_id = nir_load_work_group_id(&b);
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b, 32);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
nir_ssa_def *block_size = nir_imm_ivec4(&b,
b.shader->info.cs.local_size[0],
b.shader->info.cs.local_size[1],
diff --git a/src/compiler/nir/nir_builder_opcodes_h.py
b/src/compiler/nir/nir_builder_opcodes_h.py
index 34b8c4371e1..84e5400958e 100644
--- a/src/compiler/nir/nir_builder_opcodes_h.py
+++ b/src/compiler/nir/nir_builder_opcodes_h.py
@@ -44,14 +44,16 @@ nir_${name}(nir_builder *build,
${src_decl_list(opcode.num_inputs)})
/* Generic builder for system values. */
static inline nir_ssa_def *
-nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index)
+nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index,
+ unsigned bit_size)
{
nir_intrinsic_instr *load = nir_intrinsic_instr_create(build->shader, op);
load->num_components = nir_intrinsic_infos[op].dest_components;
load->const_index[0] = index;
nir_ssa_dest_init(&load->instr, &load->dest,
- nir_intrinsic_infos[op].dest_components, 32, NULL);
+ nir_intrinsic_infos[op].dest_components, bit_size, NULL);
nir_builder_instr_insert(build, &load->instr);
+
return &load->dest.ssa;
}
@@ -60,6 +62,8 @@ def sysval_decl_list(opcode):
res = ''
if opcode.indices:
res += ', unsigned ' + opcode.indices[0].lower()
+ if len(opcode.bit_sizes) > 1:
+ res += ', unsigned bit_size'
return res
def sysval_arg_list(opcode):
@@ -68,6 +72,13 @@ def sysval_arg_list(opcode):
args.append(opcode.indices[0].lower())
else:
args.append('0')
+
+ if len(opcode.bit_sizes) == 1:
+ bit_size = opcode.bit_sizes[0]
+ args.append(str(bit_size))
+ else:
+ args.append('bit_size')
+
return ', '.join(args)
%>
diff --git a/src/compiler/nir/nir_intrinsics.py
b/src/compiler/nir/nir_intrinsics.py
index 9ada44aad8a..6bcce81b14e 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -477,11 +477,11 @@ system_value("tess_coord", 3)
system_value("tess_level_outer", 4)
system_value("tess_level_inner", 2)
system_value("patch_vertices_in", 1)
-system_value("local_invocation_id", 3)
+system_value("local_invocation_id", 3, bit_sizes=[32, 64])
system_value("local_invocation_index", 1)
-system_value("work_group_id", 3)
+system_value("work_group_id", 3, bit_sizes=[32, 64])
system_value("user_clip_plane", 4, indices=[UCP_ID])
-system_value("num_work_groups", 3)
+system_value("num_work_groups", 3, bit_sizes=[32, 64])
system_value("helper_invocation", 1)
system_value("alpha_ref_float", 1)
system_value("layer_id", 1)
@@ -495,8 +495,8 @@ system_value("subgroup_le_mask", 0)
system_value("subgroup_lt_mask", 0)
system_value("num_subgroups", 1)
system_value("subgroup_id", 1)
-system_value("local_group_size", 3)
-system_value("global_invocation_id", 3)
+system_value("local_group_size", 3, bit_sizes=[32, 64])
+system_value("global_invocation_id", 3, bit_sizes=[32, 64])
system_value("work_dim", 1)
# Blend constant color values. Float values are clamped.#
diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir/nir_lower_system_values.c
index fbc40573579..c4ad05a0d21 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -29,23 +29,33 @@
#include "nir_builder.h"
static nir_ssa_def*
-build_local_group_size(nir_builder *b)
+build_local_group_size(nir_builder *b, unsigned bit_size)
{
+ const nir_intrinsic_info *info =
+ &nir_intrinsic_infos[nir_intrinsic_load_local_group_size];
nir_ssa_def *local_size;
+ assert(info->bit_sizes & bit_size);
+
/*
* If the local work group size is variable it can't be lowered at this
* point, but its intrinsic can still be used.
*/
if (b->shader->info.cs.local_size_variable) {
- local_size = nir_load_local_group_size(b);
+ local_size = nir_load_local_group_size(b, bit_size);
} else {
nir_const_value local_size_const;
memset(&local_size_const, 0, sizeof(local_size_const));
- local_size_const.u32[0] = b->shader->info.cs.local_size[0];
- local_size_const.u32[1] = b->shader->info.cs.local_size[1];
- local_size_const.u32[2] = b->shader->info.cs.local_size[2];
- local_size = nir_build_imm(b, 3, 32, local_size_const);
+ if (bit_size == 32) {
+ local_size_const.u32[0] = b->shader->info.cs.local_size[0];
+ local_size_const.u32[1] = b->shader->info.cs.local_size[1];
+ local_size_const.u32[2] = b->shader->info.cs.local_size[2];
+ } else {
+ local_size_const.u64[0] = b->shader->info.cs.local_size[0];
+ local_size_const.u64[1] = b->shader->info.cs.local_size[1];
+ local_size_const.u64[2] = b->shader->info.cs.local_size[2];
+ }
+ local_size = nir_build_imm(b, 3, bit_size, local_size_const);
}
return local_size;
@@ -81,6 +91,7 @@ convert_block(nir_block *block, nir_builder *b)
b->cursor = nir_after_instr(&load_deref->instr);
+ unsigned bit_size = nir_dest_bit_size(load_deref->dest);
nir_ssa_def *sysval = NULL;
switch (var->data.location) {
case SYSTEM_VALUE_GLOBAL_INVOCATION_ID: {
@@ -89,9 +100,9 @@ convert_block(nir_block *block, nir_builder *b)
* "The value of gl_GlobalInvocationID is equal to
* gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID"
*/
- nir_ssa_def *group_size = build_local_group_size(b);
- nir_ssa_def *group_id = nir_load_work_group_id(b);
- nir_ssa_def *local_id = nir_load_local_invocation_id(b);
+ nir_ssa_def *group_size = build_local_group_size(b, bit_size);
+ nir_ssa_def *group_id = nir_load_work_group_id(b, bit_size);
+ nir_ssa_def *local_id = nir_load_local_invocation_id(b, bit_size);
sysval = nir_iadd(b, nir_imul(b, group_id, group_size), local_id);
break;
@@ -111,7 +122,7 @@ convert_block(nir_block *block, nir_builder *b)
* gl_WorkGroupSize.y + gl_LocalInvocationID.y *
* gl_WorkGroupSize.x + gl_LocalInvocationID.x"
*/
- nir_ssa_def *local_id = nir_load_local_invocation_id(b);
+ nir_ssa_def *local_id = nir_load_local_invocation_id(b, bit_size);
nir_ssa_def *size_x =
nir_imm_int(b, b->shader->info.cs.local_size[0]);
@@ -127,7 +138,7 @@ convert_block(nir_block *block, nir_builder *b)
}
case SYSTEM_VALUE_LOCAL_GROUP_SIZE: {
- sysval = build_local_group_size(b);
+ sysval = build_local_group_size(b, bit_size);
break;
}
@@ -201,8 +212,8 @@ convert_block(nir_block *block, nir_builder *b)
break;
case SYSTEM_VALUE_GLOBAL_GROUP_SIZE: {
- nir_ssa_def *group_size = build_local_group_size(b);
- nir_ssa_def *num_work_groups = nir_load_num_work_groups(b);
+ nir_ssa_def *group_size = build_local_group_size(b, bit_size);
+ nir_ssa_def *num_work_groups = nir_load_num_work_groups(b, bit_size);
sysval = nir_imul(b, group_size, num_work_groups);
break;
}
@@ -214,8 +225,7 @@ convert_block(nir_block *block, nir_builder *b)
if (sysval == NULL) {
nir_intrinsic_op sysval_op =
nir_intrinsic_from_system_value(var->data.location);
- sysval = nir_load_system_value(b, sysval_op, 0);
- sysval->bit_size = load_deref->dest.ssa.bit_size;
+ sysval = nir_load_system_value(b, sysval_op, 0,
load_deref->dest.ssa.bit_size);
}
nir_ssa_def_rewrite_uses(&load_deref->dest.ssa, nir_src_for_ssa(sysval));
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 0ad274b535a..b108c05d895 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -517,7 +517,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned
file, unsigned index,
nir_ssa_def *tgsi_frontface[4] = {
nir_bcsel(&c->build,
nir_load_system_value(&c->build,
- nir_intrinsic_load_front_face, 0),
+ nir_intrinsic_load_front_face, 0,
32),
nir_imm_float(&c->build, 1.0),
nir_imm_float(&c->build, -1.0)),
nir_imm_float(&c->build, 0.0),
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
index 60eccb4fc00..f80558722a1 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
@@ -130,7 +130,7 @@ vc4_blend_channel_f(nir_builder *b,
return nir_load_system_value(b,
nir_intrinsic_load_blend_const_color_r_float +
channel,
- 0);
+ 0, 32);
case PIPE_BLENDFACTOR_CONST_ALPHA:
return nir_load_blend_const_color_a_float(b);
case PIPE_BLENDFACTOR_ZERO:
@@ -148,7 +148,7 @@ vc4_blend_channel_f(nir_builder *b,
nir_load_system_value(b,
nir_intrinsic_load_blend_const_color_r_float +
channel,
- 0));
+ 0, 32));
case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
return nir_fsub(b, nir_imm_float(b, 1.0),
nir_load_blend_const_color_a_float(b));
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 80fa5a1a81f..8e5b7fd9e8c 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -978,7 +978,7 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct
brw_compiler *compile
nir_intrinsic_instr *store;
nir_ssa_def *zero = nir_imm_int(&b, 0);
nir_ssa_def *invoc_id =
- nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
+ nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0, 32);
nir->info.inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
--
2.19.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
