From: Dave Airlie <airl...@redhat.com>
As pointed out by Marek, if we have only one cb, we may as well add this
single register write here rather than adding it in the draw loop.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/gallium/drivers/r600/evergreen_state.c | 8 ++++++--
src/gallium/drivers/r600/r600_pipe.h | 1 -
src/gallium/drivers/r600/r600_state.c | 8 ++++++--
src/gallium/drivers/r600/r600_state_common.c | 10 ----------
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 758f6cf..6cd0978 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1470,8 +1470,12 @@ static void evergreen_cb(struct r600_context *rctx,
struct r600_pipe_state *rsta
}
rctx->alpha_ref_dirty = true;
- if (cb == 0)
- rctx->color0_format = color_info;
+ /* for possible dual-src MRT */
+ if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
+ r600_pipe_state_add_reg_bo(rstate,
+ R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
+ color_info, &rtex->resource,
RADEON_USAGE_READWRITE);
+ }
offset += r600_resource_va(rctx->context.screen,
state->cbufs[cb]->texture);
offset >>= 8;
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index cad80f9..c161d93 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -358,7 +358,6 @@ struct r600_context {
bool vertex_buffers_dirty;
boolean dual_src_blend;
- unsigned color0_format;
};
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom
*atom)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 49aedd4..de4466d 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1509,8 +1509,12 @@ static void r600_cb(struct r600_context *rctx, struct
r600_pipe_state *rstate,
color_info |=
S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
}
- if (cb == 0)
- rctx->color0_format = color_info;
+ /* for possible dual-src MRT write color info 1 */
+ if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
+ r600_pipe_state_add_reg_bo(rstate,
+ R_0280A0_CB_COLOR0_INFO + 1 * 4,
+ color_info, &rtex->resource,
RADEON_USAGE_READWRITE);
+ }
r600_pipe_state_add_reg_bo(rstate,
R_028040_CB_COLOR0_BASE + cb * 4,
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 40a33f1..0ed5939 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -813,11 +813,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt,
R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL,
0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL,
0);
-
- if (rctx->chip_class <= R700)
- r600_pipe_state_add_reg(&rctx->vgt,
R_0280A4_CB_COLOR1_INFO, 0);
- else
- r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0);
}
rctx->vgt.nregs = 0;
@@ -847,11 +842,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *dinfo)
rctx->vs_shader->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable &
0x3F));
- if (rctx->dual_src_blend) {
- r600_pipe_state_mod_reg(&rctx->vgt,
- rctx->color0_format);
- }
-
r600_context_pipe_state_set(rctx, &rctx->vgt);
/* Emit states (the function expects that we emit at most 17 dwords
here). */
--
1.7.7.6
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