CC: Jason Ekstrand <ja...@jlekstrand.net>
CC: Nanley Chery <nanley.g.ch...@intel.com>
CC: Anuj Phogat <anuj.pho...@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/intel/isl/isl_gen8.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c
index 2199b8d22d..f9a424dd48 100644
--- a/src/intel/isl/isl_gen8.c
+++ b/src/intel/isl/isl_gen8.c
@@ -87,6 +87,38 @@ isl_gen8_choose_msaa_layout(const struct isl_device *dev,
return true;
}
+static void
+gen11_wa_1604596806(const struct isl_surf_init_info *restrict info,
+ enum isl_tiling tiling, const uint32_t bpb,
+ struct isl_extent3d *align_el)
+
+{
+ /* Don't try to apply the workaround for depth or stencil. See the Ice Lake
+ * BSpec: Shared Functions - vol5c Shared Functions - RENDER_SURFACE_STATE:
+ *
+ * This field is intended to be set to HALIGN_8 only if the surface was
+ * rendered as a depth buffer with Z16 format or a stencil buffer. In this
+ * case it must be set to HALIGN_8 since these surfaces support only
+ * alignment of 8. For Z32 formats it must be set ot HALIGN_4. Use of
+ * HALIGN_8 for other surfaces is supported, but increases memory usage.
+ */
+ if (info->usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT))
+ return;
+
+ /* See the Ice Lake BSpec: GEN:BUG:1604596806 : Pixel Corruption in
+ * subspan combining (8x4 combining) scenarios if halign=4
+ *
+ * Shared Functions - vol5c Shared Functions - RENDER_SURFACE_STATE:
+ *
+ * For surface format = 32 bpp, num_multisamples = 1 , MIpcount > 0 and
+ * surface walk = TiledY, HALIGN must be programmed to 8
+ */
+ if (tiling == ISL_TILING_Y0 && bpb == 32 && info->samples == 1) {
+ assert(align_el->w == 4);
+ align_el->w = 8;
+ }
+}
+
void
isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict
info,
@@ -174,4 +206,7 @@ isl_gen8_choose_image_alignment_el(const struct isl_device
*dev,
const uint32_t halign = needs_halign16 ? 16 : 4;
*image_align_el = isl_extent3d(halign, valign, 1);
+
+ if (!needs_halign16 && dev->info->gen == 11)
+ gen11_wa_1604596806(info, tiling, fmtl->bpb, image_align_el);
}
--
2.17.1
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