From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_clear.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index 520e5b94f4a..8aa3355afc8 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -425,51 +425,50 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
*/
if (tex->buffer.b.is_shared &&
!(tex->buffer.external_usage &
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
if (sctx->chip_class <= VI &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D
&&
!sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
- bool need_decompress_pass = false;
-
/* Use a slow clear for small surfaces where the cost of
* the eliminate pass can be higher than the benefit of fast
* clear. The closed driver does this, but the numbers may
differ.
*
* This helps on both dGPUs and APUs, even small APUs like
Mullins.
*/
bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
tex->buffer.b.b.width0 *
tex->buffer.b.b.height0 <= 512 * 512;
+ bool eliminate_needed = false;
+ bool fmask_decompress_needed = false;
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.
*/
if (sctx->family == CHIP_STONEY && !too_small) {
vi_separate_dcc_try_enable(sctx, tex);
/* RB+ isn't supported with a CMASK clear only on
Stoney,
* so all clears are considered to be hypothetically
slow
* clears, which is weighed when determining whether to
* enable separate DCC.
*/
if (tex->dcc_gather_statistics) /* only for Stoney */
tex->num_slow_clears++;
}
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
- bool eliminate_needed;
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
/* This can happen with mipmapping or MSAA. */
if (sctx->chip_class == VI &&
!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
continue;
if
(!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
@@ -484,28 +483,24 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
/* DCC fast clear with MSAA should clear CMASK to 0xC.
*/
if (tex->buffer.b.b.nr_samples >= 2 &&
tex->cmask_buffer) {
/* TODO: This doesn't work with MSAA. */
if (eliminate_needed)
continue;
uint32_t clear_value = 0xCCCCCCCC;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask_offset,
tex->surface.cmask_size,
&clear_value, 4,
SI_COHERENCY_CB_META);
- need_decompress_pass = true;
+ fmask_decompress_needed = true;
}
vi_dcc_clear_level(sctx, tex, 0, reset_value);
-
- if (eliminate_needed)
- need_decompress_pass = true;
-
tex->separate_dcc_dirty = true;
} else {
if (too_small)
continue;
/* 128-bit formats are unusupported */
if (tex->surface.bpe > 8) {
continue;
}
@@ -516,37 +511,38 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
/* ensure CMASK is enabled */
si_alloc_separate_cmask(sctx->screen, tex);
if (!tex->cmask_buffer)
continue;
/* Do the fast clear. */
uint32_t clear_value = 0;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask_offset,
tex->surface.cmask_size,
&clear_value, 4, SI_COHERENCY_CB_META);
- need_decompress_pass = true;
+ eliminate_needed = true;
}
- if (need_decompress_pass &&
+ if ((eliminate_needed || fmask_decompress_needed) &&
!(tex->dirty_level_mask & (1 << level))) {
tex->dirty_level_mask |= 1 << level;
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
}
/* We can change the micro tile mode before a full clear. */
si_set_optimal_micro_tile_mode(sctx->screen, tex);
+ *buffers &= ~clear_bit;
+
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
sctx->framebuffer.dirty_cbufs |= 1 << i;
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
}
- *buffers &= ~clear_bit;
}
}
static void si_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
struct pipe_surface *zsbuf = fb->zsbuf;
--
2.17.1
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