On Thu, Oct 25, 2018 at 6:25 PM <nanleych...@gmail.com> wrote:
> From: Nanley Chery <nanley.g.ch...@intel.com>
>
> Follow the restriction of making sure the clear value is between the min
> and max values defined in CC_VIEWPORT. Avoids a simulator warning for
> some piglit tests, one of them being:
>
> ./bin/depthstencil-render-miplevels 146 d=z32f_s8
>
> Jason found this to make a GPU hang go away on SKL.
>
It wasn't really hangs. It was just incorrect clearing. The hangs may be
related but I have no proof of that. With the commit message adjusted
accordingly, this patch is
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Tested-by: Jason Ekstrand <ja...@jlekstrand.net>
> Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
> ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
> ---
> src/intel/blorp/blorp_genX_exec.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/intel/blorp/blorp_genX_exec.h
> b/src/intel/blorp/blorp_genX_exec.h
> index 50341ab0ecf..7a8c45dbee5 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -1628,6 +1628,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
> */
> blorp_emit_3dstate_multisample(batch, params);
>
> + /* From the BDW PRM Volume 7, Depth Buffer Clear:
> + *
> + * The clear value must be between the min and max depth values
> + * (inclusive) defined in the CC_VIEWPORT. If the depth buffer
> format is
> + * D32_FLOAT, then +/-DENORM values are also allowed.
> + *
> + * Set the bounds to match our hardware limits, [0.0, 1.0].
> + */
> + if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
> + assert(params->depth.clear_color.f32[0] >= 0.0f);
> + assert(params->depth.clear_color.f32[0] <= 1.0f);
> + blorp_emit_cc_viewport(batch);
> + }
> +
> /* If we can't alter the depth stencil config and multiple layers are
> * involved, the HiZ op will fail. This is because the op requires
> that a
> * new config is emitted for each additional layer.
> --
> 2.19.0
>
>
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