Identifier bits in the dispatch header have changed. See Bspec:
SINGLE_PATCH Payload:
3D Pipeline Stages - 3D Pipeline Geometry -
Hull Shader (HS) Stage IVB+ - Payloads IVB+
Fixes:
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
CC: Anuj Phogat <anuj.pho...@gmail.com>
CC: Mark Janes <mark.a.ja...@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/intel/compiler/brw_fs.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 23a25fedca5..757147b01ec 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6593,14 +6593,18 @@ fs_visitor::run_tcs_single_patch()
if (tcs_prog_data->instances == 1) {
invocation_id = channels_ud;
} else {
+ const unsigned invocation_id_mask = devinfo->gen >= 11 ?
+ INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
+ const unsigned invocation_id_shift = devinfo->gen >= 11 ? 16 : 17;
+
invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
/* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
fs_reg instance_times_8 = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)),
- brw_imm_ud(INTEL_MASK(23, 17)));
- bld.SHR(instance_times_8, t, brw_imm_ud(17 - 3));
+ brw_imm_ud(invocation_id_mask));
+ bld.SHR(instance_times_8, t, brw_imm_ud(invocation_id_shift - 3));
bld.ADD(invocation_id, instance_times_8, channels_ud);
}
--
2.17.1
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