Thanks. I pushed the series.

Please see also this commit:
https://cgit.freedesktop.org/mesa/mesa/commit/?id=86f004bdfcc1c14ace99f5fccf540c0d813d2254

I added it because the logic was broken for 64-bit reg_saved.

Marek
On Wed, Oct 3, 2018 at 11:55 AM Sonny Jiang <sonny.ji...@amd.com> wrote:
>
> Signed-off-by: Sonny Jiang <sonny.ji...@amd.com>
> ---
>  src/gallium/drivers/radeonsi/si_gfx_cs.c        |  1 +
>  src/gallium/drivers/radeonsi/si_shader.h        |  1 +
>  src/gallium/drivers/radeonsi/si_state.h         |  1 +
>  src/gallium/drivers/radeonsi/si_state_shaders.c | 17 +++++++++++++++--
>  4 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c 
> b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> index 532a6365bf..3ddd7864d1 100644
> --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
> +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> @@ -377,6 +377,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
>                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] 
>  = 0x00000000;
>                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 
> 0xffffffff;
>                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 
> 0x00000000;
> +               
> ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 
> 0x0000001e; /* From VI */
>
>                 /* Set all saved registers state to saved. */
>                 ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
> diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
> b/src/gallium/drivers/radeonsi/si_shader.h
> index 49b1ccd582..09dd558d78 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.h
> +++ b/src/gallium/drivers/radeonsi/si_shader.h
> @@ -689,6 +689,7 @@ struct si_shader {
>
>         /*For save precompute registers value */
>         unsigned vgt_tf_param; /* VGT_TF_PARAM */
> +       unsigned vgt_vertex_reuse_block_cntl; /* VGT_VERTEX_REUSE_BLOCK_CNTL 
> */
>  };
>
>  struct si_shader_part {
> diff --git a/src/gallium/drivers/radeonsi/si_state.h 
> b/src/gallium/drivers/radeonsi/si_state.h
> index 54b03e0992..fffc63680d 100644
> --- a/src/gallium/drivers/radeonsi/si_state.h
> +++ b/src/gallium/drivers/radeonsi/si_state.h
> @@ -313,6 +313,7 @@ enum si_tracked_reg {
>
>         SI_TRACKED_CB_SHADER_MASK,
>         SI_TRACKED_VGT_TF_PARAM,
> +       SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
>
>         SI_NUM_TRACKED_REGS,
>  };
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index 217ef4471c..50ce50cfb0 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -440,8 +440,8 @@ static void polaris_set_vgt_vertex_reuse(struct si_screen 
> *sscreen,
>                     PIPE_TESS_SPACING_FRACTIONAL_ODD)
>                         vtx_reuse_depth = 14;
>
> -               si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
> -                              vtx_reuse_depth);
> +               assert(pm4->shader);
> +               pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
>         }
>  }
>
> @@ -574,6 +574,10 @@ static void si_emit_shader_es(struct si_context *sctx)
>                                            SI_TRACKED_VGT_TF_PARAM,
>                                            shader->vgt_tf_param);
>
> +       if (shader->vgt_vertex_reuse_block_cntl)
> +               radeon_opt_set_context_reg(sctx, 
> R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                          
> SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                          
> shader->vgt_vertex_reuse_block_cntl);
>  }
>
>  static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
> @@ -813,6 +817,10 @@ static void si_emit_shader_gs(struct si_context *sctx)
>                         radeon_opt_set_context_reg(sctx, 
> R_028B6C_VGT_TF_PARAM,
>                                                    SI_TRACKED_VGT_TF_PARAM,
>                                                    shader->vgt_tf_param);
> +               if (shader->vgt_vertex_reuse_block_cntl)
> +                       radeon_opt_set_context_reg(sctx, 
> R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                                  
> SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                                  
> shader->vgt_vertex_reuse_block_cntl);
>         }
>  }
>
> @@ -981,6 +989,11 @@ static void si_emit_shader_vs(struct si_context *sctx)
>                 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
>                                            SI_TRACKED_VGT_TF_PARAM,
>                                            shader->vgt_tf_param);
> +
> +       if (shader->vgt_vertex_reuse_block_cntl)
> +               radeon_opt_set_context_reg(sctx, 
> R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                          
> SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
> +                                          
> shader->vgt_vertex_reuse_block_cntl);
>  }
>
>  /**
> --
> 2.17.1
>
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