On Mon, Sep 10, 2018 at 6:30 PM, Bas Nieuwenhuizen
<b...@basnieuwenhuizen.nl> wrote:
> On Mon, Sep 10, 2018 at 8:05 PM Jason Ekstrand <ja...@jlekstrand.net> wrote:
>>
>> ---
>> src/compiler/spirv/spirv_to_nir.c | 170 ++++++++++++++++++------------
>> 1 file changed, 103 insertions(+), 67 deletions(-)
>>
>> diff --git a/src/compiler/spirv/spirv_to_nir.c
>> b/src/compiler/spirv/spirv_to_nir.c
>> index 96224354057..3378641513c 100644
>> --- a/src/compiler/spirv/spirv_to_nir.c
>> +++ b/src/compiler/spirv/spirv_to_nir.c
>> @@ -2314,6 +2314,79 @@ fill_common_atomic_sources(struct vtn_builder *b,
>> SpvOp opcode,
>> }
>> }
>>
>> +static void
>> +vtn_emit_barrier(struct vtn_builder *b, nir_intrinsic_op op)
>> +{
>> + nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->shader, op);
>> + nir_builder_instr_insert(&b->nb, &intrin->instr);
>> +}
>> +
>> +static void
>> +vtn_emit_memory_barrier(struct vtn_builder *b, SpvScope scope,
>> + SpvMemorySemanticsMask semantics)
>> +{
>> + static const SpvMemorySemanticsMask all_memory_semantics =
>> + SpvMemorySemanticsUniformMemoryMask |
>> + SpvMemorySemanticsWorkgroupMemoryMask |
>> + SpvMemorySemanticsAtomicCounterMemoryMask |
>> + SpvMemorySemanticsImageMemoryMask |
>> + SpvMemorySemanticsOutputMemoryKHRMask |
>> + SpvMemorySemanticsMakeAvailableKHRMask |
>> + SpvMemorySemanticsMakeVisibleKHRMask;
>> +
>> + /* If we're not actually doing a memory barrier, bail */
>> + if (!(semantics & all_memory_semantics))
>> + return;
>> +
>> + /* GL and Vulkan don't have these */
>> + vtn_assert(scope != SpvScopeCrossDevice);
>> +
>> + if (scope == SpvScopeSubgroup)
>> + return; /* Nothing to do here */
>
> I don't think doing nothing here works for AMD, I think in some cases
> we can have some hardware reordering.
>
> +cc Marek to confirm.
Yes, I think we need to wait for all memory instructions to finish at
a subgroup barrier.
Marek
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