Noticed while working in this area. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_pipeline.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1741d5e9047..e362c380453 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1575,7 +1575,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
const struct radv_gs_sta
unsigned num_se = device->physical_device->rad_info.max_se;
unsigned wave_size = 64;
unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
- unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register
(per SE) */
+ /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
+ * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
+ */
+ unsigned gs_vertex_reuse =
+ device->physical_device->rad_info.chip_class >= VI ? 32 : 16;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
--
2.18.0
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