From: Marek Olšák <marek.ol...@amd.com>
Windows doesn't have thrd_current.
---
src/gallium/auxiliary/util/u_helpers.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_helpers.c
b/src/gallium/auxiliary/util/u_helpers.c
index f773360..8095242 100644
--- a/src/gallium/auxiliary/util/u_helpers.c
+++ b/src/gallium/auxiliary/util/u_helpers.c
@@ -127,20 +127,21 @@ util_upload_index_buffer(struct pipe_context *pipe,
* The function pins the current thread and driver threads to a group of
* CPU cores that share the same L3 cache. This is needed for good multi-
* threading performance on AMD Zen CPUs.
*
* \param upper_thread thread in the state tracker that also needs to be
* pinned.
*/
void
util_context_thread_changed(struct pipe_context *ctx, thrd_t *upper_thread)
{
+#ifdef HAVE_PTHREAD
thrd_t current = thrd_current();
int cache = util_get_L3_for_pinned_thread(current,
util_cpu_caps.cores_per_L3);
/* If the main thread is not pinned, choose the L3 cache. */
if (cache == -1) {
unsigned num_caches = util_cpu_caps.nr_cpus /
util_cpu_caps.cores_per_L3;
static unsigned last_cache;
@@ -151,20 +152,21 @@ util_context_thread_changed(struct pipe_context *ctx,
thrd_t *upper_thread)
/* Tell the driver to pin its threads to the same L3 cache. */
if (ctx->set_context_param) {
ctx->set_context_param(ctx, PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
cache);
}
/* Do the same for the upper level thread if there is any (e.g. glthread) */
if (upper_thread)
util_pin_thread_to_L3(*upper_thread, cache, util_cpu_caps.cores_per_L3);
+#endif
}
/* This is a helper for hardware bring-up. Don't remove. */
struct pipe_query *
util_begin_pipestat_query(struct pipe_context *ctx)
{
struct pipe_query *q =
ctx->create_query(ctx, PIPE_QUERY_PIPELINE_STATISTICS, 0);
if (!q)
return NULL;
--
2.7.4
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