Documentation says this bit is gone and we've indeed set all the slm
field to 0 in common/gen_l3_config.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/genxml/gen11.xml | 1 -
src/intel/vulkan/genX_cmd_buffer.c | 6 ++++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1b3befbbfc9..f497c2df825 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3544,7 +3544,6 @@
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
- <field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 16168d415c3..70d6db621be 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1548,8 +1548,6 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer,
gen_dump_l3_config(cfg, stderr);
}
- const bool has_slm = cfg->n[GEN_L3P_SLM];
-
/* According to the hardware docs, the L3 partitioning can only be changed
* while the pipeline is completely drained and the caches are flushed,
* which involves a first PIPE_CONTROL flush which stalls the pipeline...
@@ -1591,13 +1589,17 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer,
pc.CommandStreamerStallEnable = true;
}
+ MAYBE_UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
+
#if GEN_GEN >= 8
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
uint32_t l3cr;
anv_pack_struct(&l3cr, GENX(L3CNTLREG),
+#if GEN_GEN < 11
.SLMEnable = has_slm,
+#endif
.URBAllocation = cfg->n[GEN_L3P_URB],
.ROAllocation = cfg->n[GEN_L3P_RO],
.DCAllocation = cfg->n[GEN_L3P_DC],
--
2.19.0.rc1
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