The original patch was from Ilia Mirkin. See the link at https://patchwork.freedesktop.org/series/30443/. This one rebased that patch, and it can pass the deqp cts right now. --- src/compiler/shader_info.h | 1 + src/compiler/spirv/spirv_to_nir.c | 9 +++++++++ src/intel/vulkan/anv_extensions.py | 1 + src/intel/vulkan/anv_pipeline.c | 1 + src/intel/vulkan/genX_pipeline.c | 13 +++++++++++-- 5 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 3b95d5962c..e9ca222dea 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/shader_info.h @@ -59,6 +59,7 @@ struct spirv_supported_capabilities { bool stencil_export; bool atomic_storage; bool storage_8bit; + bool post_depth_coverage; }; typedef struct shader_info { diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index b92197b39b..7ac51a0107 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -3542,6 +3542,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, SpvOp opcode, spv_check_supported(stencil_export, cap); break; + case SpvCapabilitySampleMaskPostDepthCoverage: + spv_check_supported(post_depth_coverage, cap); + break; + default: vtn_fail("Unhandled capability"); } @@ -3609,6 +3613,11 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point, b->shader->info.fs.early_fragment_tests = true; break; + case SpvExecutionModePostDepthCoverage: + vtn_assert(b->shader->info.stage == MESA_SHADER_FRAGMENT); + b->shader->info.fs.post_depth_coverage = true; + break; + case SpvExecutionModeInvocations: vtn_assert(b->shader->info.stage == MESA_SHADER_GEOMETRY); b->shader->info.gs.invocations = MAX2(1, mode->literals[0]); diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index adc1d75898..ea837744b4 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/intel/vulkan/anv_extensions.py @@ -124,6 +124,7 @@ EXTENSIONS = [ Extension('VK_EXT_shader_viewport_index_layer', 1, True), Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen >= 9'), Extension('VK_EXT_vertex_attribute_divisor', 2, True), + Extension('VK_EXT_post_depth_coverage', 1, 'device->info.gen >= 9'), ] class VkVersion: diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 95a686f783..e91c146aad 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -155,6 +155,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline, .subgroup_vote = true, .stencil_export = device->instance->physicalDevice.info.gen >= 9, .storage_8bit = device->instance->physicalDevice.info.gen >= 8, + .post_depth_coverage = device->instance->physicalDevice.info.gen >= 9, }, }; diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 0821d71c9f..4db1e27a3a 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1565,6 +1565,16 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline, return; } +#if GEN_GEN >= 9 + uint32_t coverage = ICMS_NONE; + if (wm_prog_data->uses_sample_mask) { + if (wm_prog_data->post_depth_coverage) + coverage = ICMS_DEPTH_COVERAGE; + else + coverage = ICMS_INNER_CONSERVATIVE; + } +#endif + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) { ps.PixelShaderValid = true; ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0; @@ -1617,8 +1627,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline, #if GEN_GEN >= 9 ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil; ps.PixelShaderPullsBary = wm_prog_data->pulls_bary; - ps.InputCoverageMaskState = wm_prog_data->uses_sample_mask ? - ICMS_INNER_CONSERVATIVE : ICMS_NONE; + ps.InputCoverageMaskState = coverage; #else ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask; #endif -- 2.17.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev