On Wed, Jul 11, 2018 at 4:11 PM, Marek Olšák <mar...@gmail.com> wrote:
> From: Marek Olšák <marek.ol...@amd.com>
>
> ---
> include/pci_ids/radeonsi_pci_ids.h | 7 +++++++
> src/amd/addrlib/amdgpu_asic_addr.h | 2 ++
> src/amd/addrlib/gfx9/gfx9addrlib.cpp | 3 ++-
> src/amd/addrlib/gfx9/gfx9addrlib.h | 1 +
> src/amd/common/ac_llvm_util.c | 4 +++-
> src/amd/common/ac_surface.c | 4 ++++
> src/amd/common/amd_family.h | 1 +
> src/amd/common/gfx9d.h | 1 +
> src/gallium/drivers/radeonsi/si_get.c | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
> src/gallium/drivers/radeonsi/si_state.c | 1 +
> src/gallium/drivers/radeonsi/si_state_binning.c | 1 +
> 12 files changed, 26 insertions(+), 3 deletions(-)
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
>
> diff --git a/include/pci_ids/radeonsi_pci_ids.h
> b/include/pci_ids/radeonsi_pci_ids.h
> index 6386d21a19f..c8d30597230 100644
> --- a/include/pci_ids/radeonsi_pci_ids.h
> +++ b/include/pci_ids/radeonsi_pci_ids.h
> @@ -228,11 +228,18 @@ CHIPSET(0x6867, VEGA10)
> CHIPSET(0x6868, VEGA10)
> CHIPSET(0x687F, VEGA10)
> CHIPSET(0x686C, VEGA10)
>
> CHIPSET(0x69A0, VEGA12)
> CHIPSET(0x69A1, VEGA12)
> CHIPSET(0x69A2, VEGA12)
> CHIPSET(0x69A3, VEGA12)
> CHIPSET(0x69AF, VEGA12)
>
> +CHIPSET(0x66A0, VEGA20)
> +CHIPSET(0x66A1, VEGA20)
> +CHIPSET(0x66A2, VEGA20)
> +CHIPSET(0x66A3, VEGA20)
> +CHIPSET(0x66A7, VEGA20)
> +CHIPSET(0x66AF, VEGA20)
> +
> CHIPSET(0x15DD, RAVEN)
> diff --git a/src/amd/addrlib/amdgpu_asic_addr.h
> b/src/amd/addrlib/amdgpu_asic_addr.h
> index b4b8aecd42d..e5838d42a3c 100644
> --- a/src/amd/addrlib/amdgpu_asic_addr.h
> +++ b/src/amd/addrlib/amdgpu_asic_addr.h
> @@ -80,20 +80,21 @@
> #define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
> #define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
> #define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
>
> #define AMDGPU_CARRIZO_RANGE 0x01, 0x21
> #define AMDGPU_BRISTOL_RANGE 0x10, 0x21
> #define AMDGPU_STONEY_RANGE 0x61, 0xFF
>
> #define AMDGPU_VEGA10_RANGE 0x01, 0x14
> #define AMDGPU_VEGA12_RANGE 0x14, 0x28
> +#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
>
> #define AMDGPU_RAVEN_RANGE 0x01, 0x81
>
> #define AMDGPU_EXPAND_FIX(x) x
> #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
> #define AMDGPU_IN_RANGE(val, ...)
> AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
>
>
> // ASICREV_IS(eRevisionId, revisionName)
> #define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r,
> AMDGPU_##rn##_RANGE)
> @@ -121,14 +122,15 @@
> #define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
>
> #define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
> #define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
> #define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
>
> #define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
> #define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
> #define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
> #define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
> +#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
>
> #define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
>
> #endif // _AMDGPU_ASIC_ADDR_H
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> index b88d3243228..ef86c3bc7b5 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> @@ -1223,20 +1223,21 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
> ADDR_ASSERT((m_blockVarSizeLog2 == 0) ||
> ((m_blockVarSizeLog2 >= 17u) && (m_blockVarSizeLog2 <=
> 20u)));
> m_blockVarSizeLog2 = Min(Max(17u, m_blockVarSizeLog2), 20u);
>
> if ((m_rbPerSeLog2 == 1) &&
> (((m_pipesLog2 == 1) && ((m_seLog2 == 2) || (m_seLog2 == 3))) ||
> ((m_pipesLog2 == 2) && ((m_seLog2 == 1) || (m_seLog2 == 2)))))
> {
> ADDR_ASSERT(m_settings.isVega10 == FALSE);
> ADDR_ASSERT(m_settings.isRaven == FALSE);
> + ADDR_ASSERT(m_settings.isVega20 == FALSE);
>
> if (m_settings.isVega12)
> {
> m_settings.htileCacheRbConflict = 1;
> }
> }
> }
> else
> {
> valid = FALSE;
> @@ -1266,21 +1267,21 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
> UINT_32 uChipRevision) ///< [in] chip revision defined in
> "asic_family"_id.h
> {
> ChipFamily family = ADDR_CHIP_FAMILY_AI;
>
> switch (uChipFamily)
> {
> case FAMILY_AI:
> m_settings.isArcticIsland = 1;
> m_settings.isVega10 = ASICREV_IS_VEGA10_P(uChipRevision);
> m_settings.isVega12 = ASICREV_IS_VEGA12_P(uChipRevision);
> -
> + m_settings.isVega20 = ASICREV_IS_VEGA20_P(uChipRevision);
> m_settings.isDce12 = 1;
>
> if (m_settings.isVega10 == 0)
> {
> m_settings.htileAlignFix = 1;
> m_settings.applyAliasFix = 1;
> }
>
> m_settings.metaBaseAlignFix = 1;
>
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h
> b/src/amd/addrlib/gfx9/gfx9addrlib.h
> index 7c61a40880e..cf56507964c 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.h
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.h
> @@ -49,20 +49,21 @@ namespace V2
> */
> struct Gfx9ChipSettings
> {
> struct
> {
> // Asic/Generation name
> UINT_32 isArcticIsland : 1;
> UINT_32 isVega10 : 1;
> UINT_32 isRaven : 1;
> UINT_32 isVega12 : 1;
> + UINT_32 isVega20 : 1;
>
> // Display engine IP version name
> UINT_32 isDce12 : 1;
> UINT_32 isDcn1 : 1;
>
> // Misc configuration bits
> UINT_32 metaBaseAlignFix : 1;
> UINT_32 depthPipeXorDisable : 1;
> UINT_32 htileAlignFix : 1;
> UINT_32 applyAliasFix : 1;
> diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
> index 9e7a106afa5..c817f94a2d1 100644
> --- a/src/amd/common/ac_llvm_util.c
> +++ b/src/amd/common/ac_llvm_util.c
> @@ -121,34 +121,36 @@ const char *ac_get_llvm_processor_name(enum
> radeon_family family)
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> case CHIP_VEGAM:
> return "polaris11";
> case CHIP_VEGA10:
> return "gfx900";
> case CHIP_RAVEN:
> return "gfx902";
> case CHIP_VEGA12:
> return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
> + case CHIP_VEGA20:
> + return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
> default:
> return "";
> }
> }
>
> static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family
> family,
> enum
> ac_target_machine_options tm_options,
> const char **out_triple)
> {
> assert(family >= CHIP_TAHITI);
> char features[256];
> const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ?
> "amdgcn-mesa-mesa3d" : "amdgcn--";
> LLVMTargetRef target = ac_get_llvm_target(triple);
> - bool barrier_does_waitcnt = true; /* TODO: not for Vega20 */
> + bool barrier_does_waitcnt = family != CHIP_VEGA20;
>
> snprintf(features, sizeof(features),
>
> "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
> tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
> tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
> tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
> tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ?
> ",-promote-alloca" : "",
> barrier_does_waitcnt ? ",+auto-waitcnt-before-barrier" : "");
>
> LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index 9eb63bab038..959e7b3d735 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -136,20 +136,24 @@ static void addrlib_family_rev_id(enum radeon_family
> family,
> *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
> break;
> case CHIP_VEGA10:
> *addrlib_family = FAMILY_AI;
> *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
> break;
> case CHIP_VEGA12:
> *addrlib_family = FAMILY_AI;
> *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
> break;
> + case CHIP_VEGA20:
> + *addrlib_family = FAMILY_AI;
> + *addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
> + break;
> case CHIP_RAVEN:
> *addrlib_family = FAMILY_RV;
> *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
> break;
> default:
> fprintf(stderr, "amdgpu: Unknown family.\n");
> }
> }
>
> static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
> diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
> index 6410368f2f8..a282898be06 100644
> --- a/src/amd/common/amd_family.h
> +++ b/src/amd/common/amd_family.h
> @@ -88,20 +88,21 @@ enum radeon_family {
> CHIP_ICELAND,
> CHIP_CARRIZO,
> CHIP_FIJI,
> CHIP_STONEY,
> CHIP_POLARIS10,
> CHIP_POLARIS11,
> CHIP_POLARIS12,
> CHIP_VEGAM,
> CHIP_VEGA10,
> CHIP_VEGA12,
> + CHIP_VEGA20,
> CHIP_RAVEN,
> CHIP_LAST,
> };
>
> enum chip_class {
> CLASS_UNKNOWN = 0,
> R300,
> R400,
> R500,
> R600,
> diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
> index 485fd7d0fed..d18e6655d33 100644
> --- a/src/amd/common/gfx9d.h
> +++ b/src/amd/common/gfx9d.h
> @@ -5757,20 +5757,21 @@
> #define C_02883C_DISCARD_0_AREA_LINES
> 0xFFFFFFFD
> #define S_02883C_DISCARD_0_AREA_POINTS(x)
> (((unsigned)(x) & 0x1) << 2)
> #define G_02883C_DISCARD_0_AREA_POINTS(x) (((x)
> >> 2) & 0x1)
> #define C_02883C_DISCARD_0_AREA_POINTS
> 0xFFFFFFFB
> #define S_02883C_DISCARD_0_AREA_RECTANGLES(x)
> (((unsigned)(x) & 0x1) << 3)
> #define G_02883C_DISCARD_0_AREA_RECTANGLES(x) (((x)
> >> 3) & 0x1)
> #define C_02883C_DISCARD_0_AREA_RECTANGLES
> 0xFFFFFFF7
> #define S_02883C_USE_PROVOKING_ZW(x)
> (((unsigned)(x) & 0x1) << 4)
> #define G_02883C_USE_PROVOKING_ZW(x) (((x)
> >> 4) & 0x1)
> #define C_02883C_USE_PROVOKING_ZW
> 0xFFFFFFEF
> +#define R_028840_PA_STEREO_CNTL
> 0x028840
> #define R_028A00_PA_SU_POINT_SIZE
> 0x028A00
> #define S_028A00_HEIGHT(x)
> (((unsigned)(x) & 0xFFFF) << 0)
> #define G_028A00_HEIGHT(x) (((x)
> >> 0) & 0xFFFF)
> #define C_028A00_HEIGHT
> 0xFFFF0000
> #define S_028A00_WIDTH(x)
> (((unsigned)(x) & 0xFFFF) << 16)
> #define G_028A00_WIDTH(x) (((x)
> >> 16) & 0xFFFF)
> #define C_028A00_WIDTH
> 0x0000FFFF
> #define R_028A04_PA_SU_POINT_MINMAX
> 0x028A04
> #define S_028A04_MIN_SIZE(x)
> (((unsigned)(x) & 0xFFFF) << 0)
> #define G_028A04_MIN_SIZE(x) (((x)
> >> 0) & 0xFFFF)
> diff --git a/src/gallium/drivers/radeonsi/si_get.c
> b/src/gallium/drivers/radeonsi/si_get.c
> index 96ff2a9e46b..b8ee8734379 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -71,20 +71,21 @@ const char *si_get_family_name(const struct si_screen
> *sscreen)
> case CHIP_ICELAND: return "AMD ICELAND";
> case CHIP_CARRIZO: return "AMD CARRIZO";
> case CHIP_FIJI: return "AMD FIJI";
> case CHIP_STONEY: return "AMD STONEY";
> case CHIP_POLARIS10: return "AMD POLARIS10";
> case CHIP_POLARIS11: return "AMD POLARIS11";
> case CHIP_POLARIS12: return "AMD POLARIS12";
> case CHIP_VEGAM: return "AMD VEGAM";
> case CHIP_VEGA10: return "AMD VEGA10";
> case CHIP_VEGA12: return "AMD VEGA12";
> + case CHIP_VEGA20: return "AMD VEGA20";
> case CHIP_RAVEN: return "AMD RAVEN";
> default: return "AMD unknown";
> }
> }
>
> static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
> {
> struct si_screen *sscreen = (struct si_screen *)pscreen;
>
> switch (param) {
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index ac4f77a8964..d3d0c0ef075 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -885,21 +885,22 @@ struct pipe_screen *radeonsi_screen_create(struct
> radeon_winsys *ws,
> /* Determine tessellation ring info. */
> bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
> sscreen->info.family != CHIP_CARRIZO &&
> sscreen->info.family != CHIP_STONEY;
> /* This must be one less than the maximum number due to a hw
> limitation.
> * Various hardware bugs in SI, CIK, and GFX9 need this.
> */
> unsigned max_offchip_buffers_per_se;
>
> /* Only certain chips can use the maximum value. */
> - if (sscreen->info.family == CHIP_VEGA12)
> + if (sscreen->info.family == CHIP_VEGA12 ||
> + sscreen->info.family == CHIP_VEGA20)
> max_offchip_buffers_per_se = double_offchip_buffers ? 128 :
> 64;
> else
> max_offchip_buffers_per_se = double_offchip_buffers ? 127 :
> 63;
>
> unsigned max_offchip_buffers = max_offchip_buffers_per_se *
> sscreen->info.max_se;
> unsigned offchip_granularity;
>
> /* Hawaii has a bug with offchip buffers > 256 that can be worked
> * around by setting 4K granularity.
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 1214f446fc1..a51b3739f03 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -4985,20 +4985,21 @@ static void si_init_config(struct si_context *sctx)
> si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
> RADEON_PRIO_BORDER_COLORS);
>
> if (sctx->chip_class >= GFX9) {
> unsigned num_se = sscreen->info.max_se;
> unsigned pc_lines = 0;
>
> switch (sctx->family) {
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> + case CHIP_VEGA20:
> pc_lines = 4096;
> break;
> case CHIP_RAVEN:
> pc_lines = 1024;
> break;
> default:
> assert(0);
> }
>
> si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
> diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c
> b/src/gallium/drivers/radeonsi/si_state_binning.c
> index b68c637e1e2..4aad94d95f9 100644
> --- a/src/gallium/drivers/radeonsi/si_state_binning.c
> +++ b/src/gallium/drivers/radeonsi/si_state_binning.c
> @@ -394,20 +394,21 @@ void si_emit_dpbb_state(struct si_context *sctx)
> }
>
> /* Tunable parameters. Also test with DFSM enabled/disabled. */
> unsigned context_states_per_bin; /* allowed range: [0, 5] */
> unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
> unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
>
> switch (sctx->family) {
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> + case CHIP_VEGA20:
> case CHIP_RAVEN:
> /* Tuned for Raven. Vega might need different values. */
> context_states_per_bin = 5;
> persistent_states_per_bin = 31;
> fpovs_per_batch = 63;
> break;
> default:
> assert(0);
> }
>
> --
> 2.17.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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