From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_buffer.c | 16 ++++++------
src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
src/gallium/drivers/radeonsi/si_texture.c | 30 +++++++++++------------
4 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c
b/src/gallium/drivers/radeonsi/si_buffer.c
index 5c4ca5aefd2..a03a94453a4 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -334,21 +334,21 @@ static void si_invalidate_resource(struct pipe_context
*ctx,
static void *si_buffer_get_transfer(struct pipe_context *ctx,
struct pipe_resource *resource,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer,
void *data, struct r600_resource *staging,
unsigned offset)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct r600_transfer *transfer;
+ struct si_transfer *transfer;
if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
transfer = slab_alloc(&sctx->pool_transfers_unsync);
else
transfer = slab_alloc(&sctx->pool_transfers);
transfer->b.b.resource = NULL;
pipe_resource_reference(&transfer->b.b.resource, resource);
transfer->b.b.level = 0;
transfer->b.b.usage = usage;
@@ -510,31 +510,31 @@ static void *si_buffer_transfer_map(struct pipe_context
*ctx,
data += box->x;
return si_buffer_get_transfer(ctx, resource, usage, box,
ptransfer, data, NULL, 0);
}
static void si_buffer_do_flush_region(struct pipe_context *ctx,
struct pipe_transfer *transfer,
const struct pipe_box *box)
{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct si_transfer *stransfer = (struct si_transfer*)transfer;
struct r600_resource *rbuffer = r600_resource(transfer->resource);
- if (rtransfer->staging) {
+ if (stransfer->staging) {
struct pipe_resource *dst, *src;
unsigned soffset;
struct pipe_box dma_box;
dst = transfer->resource;
- src = &rtransfer->staging->b.b;
- soffset = rtransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT;
+ src = &stransfer->staging->b.b;
+ soffset = stransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT;
u_box_1d(soffset, box->width, &dma_box);
/* Copy the staging buffer into the original one. */
ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0,
&dma_box);
}
util_range_add(&rbuffer->valid_buffer_range, box->x,
box->x + box->width);
}
@@ -551,28 +551,28 @@ static void si_buffer_flush_region(struct pipe_context
*ctx,
u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
si_buffer_do_flush_region(ctx, transfer, &box);
}
}
static void si_buffer_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer *transfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct si_transfer *stransfer = (struct si_transfer*)transfer;
if (transfer->usage & PIPE_TRANSFER_WRITE &&
!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
si_buffer_do_flush_region(ctx, transfer, &transfer->box);
- r600_resource_reference(&rtransfer->staging, NULL);
- assert(rtransfer->b.staging == NULL); /* for threaded context only */
+ r600_resource_reference(&stransfer->staging, NULL);
+ assert(stransfer->b.staging == NULL); /* for threaded context only */
pipe_resource_reference(&transfer->resource, NULL);
/* Don't use pool_transfers_unsync. We are always in the driver
* thread. */
slab_free(&sctx->pool_transfers, transfer);
}
static void si_buffer_subdata(struct pipe_context *ctx,
struct pipe_resource *buffer,
unsigned usage, unsigned offset,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index b64c41f4fe6..ded8cb5eb08 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -859,21 +859,21 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
"glsl_correct_derivatives_after_discard"))
sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
sscreen->debug_flags |= DBG(SI_SCHED);
if (sscreen->debug_flags & DBG(INFO))
ac_print_gpu_info(&sscreen->info);
slab_create_parent(&sscreen->pool_transfers,
- sizeof(struct r600_transfer), 64);
+ sizeof(struct si_transfer), 64);
sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO",
-1));
if (sscreen->force_aniso >= 0) {
printf("radeonsi: Forcing anisotropy filter to %ix\n",
/* round down to a power of two */
1 << util_logbase2(sscreen->force_aniso));
}
(void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
(void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 4f18883c6a8..bd857f8a349 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -217,21 +217,21 @@ struct r600_resource {
bool TC_L2_dirty;
/* Whether this resource is referenced by bindless handles. */
bool texture_handle_allocated;
bool image_handle_allocated;
/* Whether the resource has been exported via resource_get_handle. */
unsigned external_usage; /* PIPE_HANDLE_USAGE_*
*/
};
-struct r600_transfer {
+struct si_transfer {
struct threaded_transfer b;
struct r600_resource *staging;
unsigned offset;
};
struct si_texture {
struct r600_resource buffer;
struct radeon_surf surface;
uint64_t size;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 307062daf2f..46df4aecf09 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -131,44 +131,44 @@ static void si_copy_region_with_blit(struct pipe_context
*pipe,
blit.mask = util_format_get_mask(src->format) &
util_format_get_mask(dst->format);
blit.filter = PIPE_TEX_FILTER_NEAREST;
if (blit.mask) {
pipe->blit(pipe, &blit);
}
}
/* Copy from a full GPU texture to a transfer's staging one. */
-static void si_copy_to_staging_texture(struct pipe_context *ctx, struct
r600_transfer *rtransfer)
+static void si_copy_to_staging_texture(struct pipe_context *ctx, struct
si_transfer *stransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
- struct pipe_resource *dst = &rtransfer->staging->b.b;
+ struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer;
+ struct pipe_resource *dst = &stransfer->staging->b.b;
struct pipe_resource *src = transfer->resource;
if (src->nr_samples > 1) {
si_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
src, transfer->level,
&transfer->box);
return;
}
sctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
&transfer->box);
}
/* Copy from a transfer's staging texture to a full GPU one. */
-static void si_copy_from_staging_texture(struct pipe_context *ctx, struct
r600_transfer *rtransfer)
+static void si_copy_from_staging_texture(struct pipe_context *ctx, struct
si_transfer *stransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+ struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer;
struct pipe_resource *dst = transfer->resource;
- struct pipe_resource *src = &rtransfer->staging->b.b;
+ struct pipe_resource *src = &stransfer->staging->b.b;
struct pipe_box sbox;
u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height,
transfer->box.depth, &sbox);
if (dst->nr_samples > 1) {
si_copy_region_with_blit(ctx, dst, transfer->level,
transfer->box.x, transfer->box.y,
transfer->box.z,
src, 0, &sbox);
return;
}
@@ -1643,21 +1643,21 @@ static void si_texture_invalidate_storage(struct
si_context *sctx,
static void *si_texture_transfer_map(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
struct si_texture *tex = (struct si_texture*)texture;
- struct r600_transfer *trans;
+ struct si_transfer *trans;
struct r600_resource *buf;
unsigned offset = 0;
char *map;
bool use_staging_texture = false;
assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER));
assert(box->width && box->height && box->depth);
/* Depth textures use staging unconditionally. */
if (!tex->is_depth) {
@@ -1700,21 +1700,21 @@ static void *si_texture_transfer_map(struct
pipe_context *ctx,
RADEON_USAGE_READWRITE)) {
/* It's busy. */
if (si_can_invalidate_texture(sctx->screen, tex,
usage, box))
si_texture_invalidate_storage(sctx, tex);
else
use_staging_texture = true;
}
}
- trans = CALLOC_STRUCT(r600_transfer);
+ trans = CALLOC_STRUCT(si_transfer);
if (!trans)
return NULL;
pipe_resource_reference(&trans->b.b.resource, texture);
trans->b.b.level = level;
trans->b.b.usage = usage;
trans->b.b.box = *box;
if (tex->is_depth) {
struct si_texture *staging_depth;
@@ -1822,38 +1822,38 @@ fail_trans:
r600_resource_reference(&trans->staging, NULL);
pipe_resource_reference(&trans->b.b.resource, NULL);
FREE(trans);
return NULL;
}
static void si_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct si_transfer *stransfer = (struct si_transfer*)transfer;
struct pipe_resource *texture = transfer->resource;
struct si_texture *tex = (struct si_texture*)texture;
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging) {
if (tex->is_depth && tex->buffer.b.b.nr_samples <= 1) {
ctx->resource_copy_region(ctx, texture, transfer->level,
transfer->box.x,
transfer->box.y, transfer->box.z,
- &rtransfer->staging->b.b,
transfer->level,
+ &stransfer->staging->b.b,
transfer->level,
&transfer->box);
} else {
- si_copy_from_staging_texture(ctx, rtransfer);
+ si_copy_from_staging_texture(ctx, stransfer);
}
}
- if (rtransfer->staging) {
- sctx->num_alloc_tex_transfer_bytes +=
rtransfer->staging->buf->size;
- r600_resource_reference(&rtransfer->staging, NULL);
+ if (stransfer->staging) {
+ sctx->num_alloc_tex_transfer_bytes +=
stransfer->staging->buf->size;
+ r600_resource_reference(&stransfer->staging, NULL);
}
/* Heuristic for {upload, draw, upload, draw, ..}:
*
* Flush the gfx IB if we've allocated too much texture storage.
*
* The idea is that we don't want to build IBs that use too much
* memory and put pressure on the kernel memory manager and we also
* want to make temporary and invalidated buffers go idle ASAP to
* decrease the total memory usage or make them reusable. The memory
--
2.17.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
