From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_blit.c | 4 ++--
src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
src/gallium/drivers/radeonsi/si_state.c | 28 +++++++++++------------
src/gallium/drivers/radeonsi/si_texture.c | 2 +-
4 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 23c543adbbf..82125910f4b 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -598,26 +598,26 @@ static void si_check_render_feedback_texture(struct
si_context *sctx,
unsigned last_level,
unsigned first_layer,
unsigned last_layer)
{
bool render_feedback = false;
if (!tex->dcc_offset)
return;
for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
- struct r600_surface * surf;
+ struct si_surface * surf;
if (!sctx->framebuffer.state.cbufs[j])
continue;
- surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
+ surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
if (tex == (struct si_texture *)surf->base.texture &&
surf->base.u.tex.level >= first_level &&
surf->base.u.tex.level <= last_level &&
surf->base.u.tex.first_layer <= last_layer &&
surf->base.u.tex.last_layer >= first_layer) {
render_feedback = true;
break;
}
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 629310a685d..ddd1dfbf762 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -298,21 +298,21 @@ struct si_texture {
/* Estimate of how much this color buffer is written to in units of
* full-screen draws: ps_invocations / (width * height)
* Shader kills, late Z, and blending with trivial discards make it
* inaccurate (we need to count CB updates, not PS invocations).
*/
unsigned ps_draw_ratio;
/* The number of clears since the last DCC usage analysis. */
unsigned num_slow_clears;
};
-struct r600_surface {
+struct si_surface {
struct pipe_surface base;
/* These can vary with block-compressed textures. */
uint16_t width0;
uint16_t height0;
bool color_initialized:1;
bool depth_initialized:1;
/* Misc. color flags. */
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index a7377f38745..e23666b4019 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -123,22 +123,22 @@ static void si_emit_cb_render_state(struct si_context
*sctx)
/* RB+ register settings. */
if (sctx->screen->rbplus_allowed) {
unsigned spi_shader_col_format =
sctx->ps_shader.cso ?
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
unsigned sx_ps_downconvert = 0;
unsigned sx_blend_opt_epsilon = 0;
unsigned sx_blend_opt_control = 0;
for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
- struct r600_surface *surf =
- (struct
r600_surface*)sctx->framebuffer.state.cbufs[i];
+ struct si_surface *surf =
+ (struct
si_surface*)sctx->framebuffer.state.cbufs[i];
unsigned format, swap, spi_format, colormask;
bool has_alpha, has_rgb;
if (!surf)
continue;
format = G_028C70_FORMAT(surf->cb_color_info);
swap = G_028C70_COMP_SWAP(surf->cb_color_info);
spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
colormask = (cb_target_mask >> (i * 4)) & 0xf;
@@ -2215,21 +2215,21 @@ static boolean si_is_format_supported(struct
pipe_screen *screen,
!(usage & PIPE_BIND_DEPTH_STENCIL))
retval |= PIPE_BIND_LINEAR;
return retval == usage;
}
/*
* framebuffer handling
*/
-static void si_choose_spi_color_formats(struct r600_surface *surf,
+static void si_choose_spi_color_formats(struct si_surface *surf,
unsigned format, unsigned swap,
unsigned ntype, bool is_depth)
{
/* Alpha is needed for alpha-to-coverage.
* Blending may be with or without alpha.
*/
unsigned normal = 0; /* most optimal, may not support blending or
export alpha */
unsigned alpha = 0; /* exports alpha, but may not support blending */
unsigned blend = 0; /* supports blending, but may not export alpha */
unsigned blend_alpha = 0; /* least optimal, supports blending and
exports alpha */
@@ -2333,21 +2333,21 @@ static void si_choose_spi_color_formats(struct
r600_surface *surf,
if (is_depth)
alpha = blend = blend_alpha = normal =
V_028714_SPI_SHADER_32_ABGR;
surf->spi_shader_col_format = normal;
surf->spi_shader_col_format_alpha = alpha;
surf->spi_shader_col_format_blend = blend;
surf->spi_shader_col_format_blend_alpha = blend_alpha;
}
static void si_initialize_color_surface(struct si_context *sctx,
- struct r600_surface *surf)
+ struct si_surface *surf)
{
struct si_texture *tex = (struct si_texture*)surf->base.texture;
unsigned color_info, color_attrib;
unsigned format, swap, ntype, endian;
const struct util_format_description *desc;
int firstchan;
unsigned blend_clamp = 0, blend_bypass = 0;
desc = util_format_description(surf->base.format);
for (firstchan = 0; firstchan < 4; firstchan++) {
@@ -2493,21 +2493,21 @@ static void si_initialize_color_surface(struct
si_context *sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;
/* Determine pixel shader export format */
si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
surf->color_initialized = true;
}
static void si_init_depth_surface(struct si_context *sctx,
- struct r600_surface *surf)
+ struct si_surface *surf)
{
struct si_texture *tex = (struct si_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
unsigned format, stencil_format;
uint32_t z_info, s_info;
format = si_translate_dbformat(tex->db_render_format);
stencil_format = tex->surface.has_stencil ?
V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
@@ -2689,38 +2689,38 @@ void si_update_fb_dirtiness_after_rendering(struct
si_context *sctx)
if (tex->surface.fmask_size)
tex->dirty_level_mask |= 1 << surf->u.tex.level;
if (tex->dcc_gather_statistics)
tex->separate_dcc_dirty = true;
}
}
static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state)
{
for (int i = 0; i < state->nr_cbufs; ++i) {
- struct r600_surface *surf = NULL;
+ struct si_surface *surf = NULL;
struct si_texture *tex;
if (!state->cbufs[i])
continue;
- surf = (struct r600_surface*)state->cbufs[i];
+ surf = (struct si_surface*)state->cbufs[i];
tex = (struct si_texture*)surf->base.texture;
p_atomic_dec(&tex->framebuffers_bound);
}
}
static void si_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_constant_buffer constbuf = {0};
- struct r600_surface *surf = NULL;
+ struct si_surface *surf = NULL;
struct si_texture *tex;
bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
unsigned old_nr_samples = sctx->framebuffer.nr_samples;
unsigned old_colorbuf_enabled_4bit =
sctx->framebuffer.colorbuf_enabled_4bit;
bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
bool old_has_stencil =
old_has_zsbuf &&
((struct
si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
bool unbound = false;
int i;
@@ -2734,21 +2734,21 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
tex = (struct
si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
if (tex->dcc_gather_statistics)
vi_separate_dcc_stop_query(sctx, tex);
}
/* Disable DCC if the formats are incompatible. */
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
continue;
- surf = (struct r600_surface*)state->cbufs[i];
+ surf = (struct si_surface*)state->cbufs[i];
tex = (struct si_texture*)surf->base.texture;
if (!surf->dcc_incompatible)
continue;
/* Since the DCC decompression calls back into set_framebuffer-
* _state, we need to unbind the framebuffer, so that
* vi_separate_dcc_stop_query isn't called twice with the same
* color buffer.
*/
@@ -2830,21 +2830,21 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
sctx->framebuffer.log_samples =
util_logbase2(sctx->framebuffer.nr_samples);
sctx->framebuffer.any_dst_linear = false;
sctx->framebuffer.CB_has_shader_readable_metadata = false;
sctx->framebuffer.DB_has_shader_readable_metadata = false;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
continue;
- surf = (struct r600_surface*)state->cbufs[i];
+ surf = (struct si_surface*)state->cbufs[i];
tex = (struct si_texture*)surf->base.texture;
if (!surf->color_initialized) {
si_initialize_color_surface(sctx, surf);
}
sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
sctx->framebuffer.spi_shader_col_format |=
surf->spi_shader_col_format << (i * 4);
sctx->framebuffer.spi_shader_col_format_alpha |=
@@ -2887,21 +2887,21 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
if (tex->dcc_gather_statistics) {
/* Dirty tracking must be enabled for DCC usage
analysis. */
sctx->framebuffer.compressed_cb_mask |= 1 << i;
vi_separate_dcc_start_query(sctx, tex);
}
}
struct si_texture *zstex = NULL;
if (state->zsbuf) {
- surf = (struct r600_surface*)state->zsbuf;
+ surf = (struct si_surface*)state->zsbuf;
zstex = (struct si_texture*)surf->base.texture;
if (!surf->depth_initialized) {
si_init_depth_surface(sctx, surf);
}
if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
sctx->framebuffer.DB_has_shader_readable_metadata =
true;
si_context_add_resource_size(sctx, surf->base.texture);
@@ -2965,32 +2965,32 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
sctx->need_check_render_feedback = true;
}
}
static void si_emit_framebuffer_state(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct si_texture *tex = NULL;
- struct r600_surface *cb = NULL;
+ struct si_surface *cb = NULL;
unsigned cb_color_info = 0;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
uint64_t cb_color_base, cb_color_fmask, cb_color_cmask,
cb_dcc_base;
unsigned cb_color_attrib;
if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
continue;
- cb = (struct r600_surface*)state->cbufs[i];
+ cb = (struct si_surface*)state->cbufs[i];
if (!cb) {
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i
* 0x3C,
S_028C70_FORMAT(V_028C70_COLOR_INVALID));
continue;
}
tex = (struct si_texture *)cb->base.texture;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
&tex->buffer, RADEON_USAGE_READWRITE,
tex->buffer.b.b.nr_samples > 1 ?
@@ -3139,21 +3139,21 @@ static void si_emit_framebuffer_state(struct si_context
*sctx)
if (sctx->chip_class >= VI) /*
R_028C94_CB_COLOR0_DCC_BASE */
radeon_emit(cs, cb_dcc_base);
}
}
for (; i < 8 ; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i
* 0x3C, 0);
/* ZS buffer. */
if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
- struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
+ struct si_surface *zb = (struct si_surface*)state->zsbuf;
struct si_texture *tex = (struct si_texture*)zb->base.texture;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
&tex->buffer, RADEON_USAGE_READWRITE,
zb->base.texture->nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
if (sctx->chip_class >= GFX9) {
radeon_set_context_reg_seq(cs,
R_028014_DB_HTILE_DATA_BASE, 3);
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index e0e91b27b2a..ef2f9c18fde 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -2012,21 +2012,21 @@ void vi_disable_dcc_if_incompatible_format(struct
si_context *sctx,
if (!si_texture_disable_dcc(sctx, stex))
si_decompress_dcc(sctx, stex);
}
struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *templ,
unsigned width0, unsigned height0,
unsigned width, unsigned height)
{
- struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
+ struct si_surface *surface = CALLOC_STRUCT(si_surface);
if (!surface)
return NULL;
assert(templ->u.tex.first_layer <= util_max_layer(texture,
templ->u.tex.level));
assert(templ->u.tex.last_layer <= util_max_layer(texture,
templ->u.tex.level));
pipe_reference_init(&surface->base.reference, 1);
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
--
2.17.1
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