From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_clear.c | 30 +++++++++++++------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index ef843966f2a..f366de32d0f 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -435,46 +435,48 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
*/
if (tex->buffer.b.is_shared &&
!(tex->buffer.external_usage &
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
if (sctx->chip_class <= VI &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D
&&
!sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
- /* Fast clear is the most appropriate place to enable DCC for
- * displayable surfaces.
- */
- vi_separate_dcc_try_enable(sctx, tex);
-
- /* RB+ isn't supported with a CMASK clear only on Stoney,
- * so all clears are considered to be hypothetically slow
- * clears, which is weighed when determining whether to
- * enable separate DCC.
- */
- if (tex->dcc_gather_statistics &&
- sctx->family == CHIP_STONEY)
- tex->num_slow_clears++;
-
bool need_decompress_pass = false;
/* Use a slow clear for small surfaces where the cost of
* the eliminate pass can be higher than the benefit of fast
* clear. The closed driver does this, but the numbers may
differ.
*
* This helps on both dGPUs and APUs, even small APUs like
Mullins.
*/
bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
tex->buffer.b.b.width0 *
tex->buffer.b.b.height0 <= 512 * 512;
+ /* Fast clear is the most appropriate place to enable DCC for
+ * displayable surfaces.
+ */
+ if (!too_small) {
+ vi_separate_dcc_try_enable(sctx, tex);
+
+ /* RB+ isn't supported with a CMASK clear only on
Stoney,
+ * so all clears are considered to be hypothetically
slow
+ * clears, which is weighed when determining whether to
+ * enable separate DCC.
+ */
+ if (tex->dcc_gather_statistics &&
+ sctx->family == CHIP_STONEY)
+ tex->num_slow_clears++;
+ }
+
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
bool eliminate_needed;
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
/* This can only occur with MSAA. */
if (sctx->chip_class == VI &&
--
2.17.1
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