From: Marek Olšák <marek.ol...@amd.com>

The values for the radeon winsys were copied from the kernel driver.
---
 src/amd/common/ac_gpu_info.c                  | 10 +++++++
 src/amd/common/ac_gpu_info.h                  |  1 +
 .../winsys/radeon/drm/radeon_drm_winsys.c     | 26 +++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 3442ffa6259..6bee96b9eee 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -89,20 +89,21 @@ static bool has_syncobj(int fd)
        uint64_t value;
        if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
                return false;
        return value ? true : false;
 }
 
 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                       struct radeon_info *info,
                       struct amdgpu_gpu_info *amdinfo)
 {
+       struct drm_amdgpu_info_device device_info = {};
        struct amdgpu_buffer_size_alignments alignment_info = {};
        struct amdgpu_heap_info vram, vram_vis, gtt;
        struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
        struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
        struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
        struct amdgpu_gds_resource_info gds = {};
        uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
        int r, i, j;
        drmDevicePtr devinfo;
 
@@ -118,20 +119,27 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->pci_func = devinfo->businfo.pci->func;
        drmFreeDevice(&devinfo);
 
        /* Query hardware and driver information. */
        r = amdgpu_query_gpu_info(dev, amdinfo);
        if (r) {
                fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
                return false;
        }
 
+       r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
+                             &device_info);
+       if (r) {
+               fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) 
failed.\n");
+               return false;
+       }
+
        r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
        if (r) {
                fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment 
failed.\n");
                return false;
        }
 
        r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
        if (r) {
                fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) 
failed.\n");
                return false;
@@ -291,20 +299,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->vram_size = vram.heap_size;
        info->vram_vis_size = vram_vis.heap_size;
        info->gds_size = gds.gds_total_size;
        info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
        /* The kernel can split large buffers in VRAM but not in GTT, so large
         * allocations can fail or cause buffer movement failures in the kernel.
         */
        info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 
0.7);
        /* convert the shader clock from KHz to MHz */
        info->max_shader_clock = amdinfo->max_engine_clk / 1000;
+       info->num_tcc_blocks = device_info.num_tcc_blocks;
        info->max_se = amdinfo->num_shader_engines;
        info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
        info->has_hw_decode =
                (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
        info->uvd_fw_version =
                uvd.available_rings ? uvd_version : 0;
        info->vce_fw_version =
                vce.available_rings ? vce_version : 0;
        info->uvd_enc_supported =
                uvd_enc.available_rings ? true : false;
@@ -497,20 +506,21 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    kernel_flushes_tc_l2_after_ib = %u\n", 
info->kernel_flushes_tc_l2_after_ib);
        printf("    has_indirect_compute_dispatch = %u\n", 
info->has_indirect_compute_dispatch);
        printf("    has_unaligned_shader_loads = %u\n", 
info->has_unaligned_shader_loads);
        printf("    has_sparse_vm_mappings = %u\n", 
info->has_sparse_vm_mappings);
        printf("    has_2d_tiling = %u\n", info->has_2d_tiling);
        printf("    has_read_registers_query = %u\n", 
info->has_read_registers_query);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
        printf("    num_good_compute_units = %i\n", 
info->num_good_compute_units);
+       printf("    num_tcc_blocks = %i\n", info->num_tcc_blocks);
        printf("    max_se = %i\n", info->max_se);
        printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
        printf("Render backend info:\n");
        printf("    num_render_backends = %i\n", info->num_render_backends);
        printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
        printf("    pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
        printf("    enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
        printf("    max_alignment = %u\n", (unsigned)info->max_alignment);
 
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 1201d811361..f6e09d2e13c 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -108,20 +108,21 @@ struct radeon_info {
        bool                        has_indirect_compute_dispatch;
        bool                        has_unaligned_shader_loads;
        bool                        has_sparse_vm_mappings;
        bool                        has_2d_tiling;
        bool                        has_read_registers_query;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
        uint32_t                    max_shader_clock;
        uint32_t                    num_good_compute_units;
+       uint32_t                    num_tcc_blocks;
        uint32_t                    max_se; /* shader engines */
        uint32_t                    max_sh_per_se; /* shader arrays per shader 
engine */
 
        /* Render backends (color + depth blocks). */
        uint32_t                    r300_num_gb_pipes;
        uint32_t                    r300_num_z_pipes;
        uint32_t                    r600_gb_backend_map; /* R600 harvest config 
*/
        bool                        r600_gb_backend_map_valid;
        uint32_t                    r600_num_banks;
        uint32_t                    gb_addr_config;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 76eea67521d..86df2ac055e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -464,20 +464,46 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
                          &ws->info.r600_max_quad_pipes);
 
     /* All GPUs have at least one compute unit */
     ws->info.num_good_compute_units = 1;
     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
                          &ws->info.num_good_compute_units);
 
     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
                          &ws->info.max_se);
 
+    switch (ws->info.family) {
+    case CHIP_HAINAN:
+    case CHIP_KABINI:
+    case CHIP_MULLINS:
+        ws->info.num_tcc_blocks = 2;
+        break;
+    case CHIP_VERDE:
+    case CHIP_OLAND:
+    case CHIP_BONAIRE:
+    case CHIP_KAVERI:
+        ws->info.num_tcc_blocks = 4;
+        break;
+    case CHIP_PITCAIRN:
+        ws->info.num_tcc_blocks = 8;
+        break;
+    case CHIP_TAHITI:
+        ws->info.num_tcc_blocks = 12;
+        break;
+    case CHIP_HAWAII:
+        ws->info.num_tcc_blocks = 16;
+        break;
+    default:
+        ws->info.num_tcc_blocks = 0;
+        break;
+    }
+
     if (!ws->info.max_se) {
         switch (ws->info.family) {
         default:
             ws->info.max_se = 1;
             break;
         case CHIP_CYPRESS:
         case CHIP_HEMLOCK:
         case CHIP_BARTS:
         case CHIP_CAYMAN:
         case CHIP_TAHITI:
-- 
2.17.1

_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Reply via email to