Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
---
src/intel/compiler/brw_eu_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 6c9dced..4f51d51 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3716,6 +3716,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits != BRW_CR0_RND_MODE_MASK) {
brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
+ brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
/* From the Skylake PRM, Volume 7, page 760:
* "Implementation Restriction on Register Access: When the control
@@ -3730,6 +3731,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits) {
brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(bits));
+ brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
}
}
--
2.5.0.400.gff86faf
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