On 09/05/18 23:18, Jason Ekstrand wrote:
>From the bspec docs for "Indirect State Pointers Disable":"At the completion of the post-sync operation associated with this pipe control packet, the indirect state pointers in the hardware are considered invalid" So the ISP disable is a post-sync type of operation which means that it should be combined with a CS stall. Without this, the simulator throws an error. Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable" Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable" Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
I dropped it thinking that because the end of batchbuffer was right after that, it wouldn't matter.
Since the similator complains : Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Thanks! - Lionel
--- src/intel/vulkan/genX_cmd_buffer.c | 1 + src/mesa/drivers/dri/i965/brw_pipe_control.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5b03dd4..d824a14 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1434,6 +1434,7 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer) } anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { pc.IndirectStatePointersDisable = true; + pc.CommandStreamerStallEnable = true; } }diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.cindex 2de5b07..53c89ad 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -366,7 +366,8 @@ gen10_emit_isp_disable(struct brw_context *brw) PIPE_CONTROL_CS_STALL, NULL, 0, 0); brw_emit_pipe_control(brw, - PIPE_CONTROL_ISP_DIS, + PIPE_CONTROL_ISP_DIS | + PIPE_CONTROL_CS_STALL, NULL, 0, 0);brw->vs.base.push_constants_dirty = true;
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