On Tuesday, May 8, 2018 11:03:38 AM PDT Scott D Phillips wrote: > Kenneth Graunke <kenn...@whitecape.org> writes: > > > On Thursday, May 3, 2018 11:51:52 PM PDT Chris Wilson wrote: > >> Quoting Kenneth Graunke (2018-05-04 02:12:39) > >> > --- > >> > src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +- > >> > 1 file changed, 1 insertion(+), 1 deletion(-) > >> > > >> > This enables it for Broadwell (with a 64-bit kernel) and Skylake+ (with > >> > any kernel). Unfortunately, it doesn't enable it for Cherryview as that > >> > has a 32-bit GTT. We could switch that over as well, but we'd have to > >> > have a single memory zone, which is kind of a special case... > >> > >> I would make it conditional on gem_param(HAS_ALIASING_PPGTT) > 1 (that > >> is on full-ppgtt, where you don't have to care about framebuffers and > >> GTT mmaps conflicting). > >> -Chris > > > > Good idea, thanks! Fixed for v2. > > I think the ALIASING_PPGTT test is actually redundant with the > I915_CONTEXT_PARAM_GTT_SIZE > 4 GiB test that you're already doing. So > patch v1 is > > Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
I think that's probably true in practice, but checking for full PPGTT makes sense, as that's what enables us to pre-assign addresses up front. I may want to support softpin on Cherryview, where GTT_SIZE == 4GB. But, I'll have to change the memory zone plan. So since the current memory zone plan requires > 4GB, we should check that too. --Ken
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