The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits. This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.
Cc: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen8_depth_state.c | 9 +++------
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index e3a355f..42ab271 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -109,8 +109,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
((hiz ? 1 : 0) << 22) |
- ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
- (brw_depth_writes_enabled(brw) << 28) |
+ ((stencil_mt != NULL) << 27) | /* Stencil Write Enable */
+ ((depth_mt != NULL) << 28) | /* Depth Write Enable */
(surftype << 29));
/* 3DSTATE_DEPTH_BUFFER dw2 */
@@ -192,9 +192,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
*/
const struct brw_tracked_state gen7_depthbuffer = {
.dirty = {
- .mesa = _NEW_BUFFERS |
- _NEW_DEPTH |
- _NEW_STENCIL,
+ .mesa = _NEW_BUFFERS,
.brw = BRW_NEW_AUX_STATE |
BRW_NEW_BATCH |
BRW_NEW_BLORP,
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 1c77218..a00e22a 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -39,9 +39,7 @@ emit_depth_packets(struct brw_context *brw,
struct intel_mipmap_tree *depth_mt,
uint32_t depthbuffer_format,
uint32_t depth_surface_type,
- bool depth_writable,
struct intel_mipmap_tree *stencil_mt,
- bool stencil_writable,
bool hiz,
uint32_t width,
uint32_t height,
@@ -64,8 +62,8 @@ emit_depth_packets(struct brw_context *brw,
BEGIN_BATCH(8);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
OUT_BATCH(depth_surface_type << 29 |
- (depth_writable ? (1 << 28) : 0) |
- (stencil_mt != NULL && stencil_writable) << 27 |
+ (depth_mt != NULL) << 28 | /* Depth Write Enable */
+ (stencil_mt != NULL) << 27 | /* Stencil Write Enable */
(hiz ? 1 : 0) << 22 |
depthbuffer_format << 18 |
(depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
@@ -204,8 +202,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
}
emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
- brw_depth_writes_enabled(brw),
- stencil_mt, brw->stencil_write_enabled,
+ stencil_mt,
hiz, width, height, depth, lod, min_array_element);
}
--
2.5.0.400.gff86faf
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