If the aux state is CLEAR and clear color value has changed, only the
surface state must be updated. The bit-pattern in the aux buffer is
exactly the same.
v2: Handle the indirect color on gen10+.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ba14136edc6..690427421cb 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1230,11 +1230,14 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
bool same_clear_color =
!intel_miptree_set_clear_color(brw, irb->mt, &ctx->Color.ClearColor);
- /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
+ /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
* is redundant and can be skipped.
*/
- if (aux_state == ISL_AUX_STATE_CLEAR && same_clear_color)
+ if (aux_state == ISL_AUX_STATE_CLEAR) {
+ if (!same_clear_color)
+ intel_miptree_update_indirect_color(brw, irb->mt);
return;
+ }
DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
--
2.16.2
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